1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P2041 Silicon/SoC Device Tree Source (pre include)
4 *
5 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019-2020 NXP
7 */
8
9/dts-v1/;
10
11/include/ "e500mc_power_isa.dtsi"
12
13/ {
14	compatible = "fsl,P2041";
15	#address-cells = <2>;
16	#size-cells = <2>;
17	interrupt-parent = <&mpic>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: PowerPC,e500mc@0 {
24			device_type = "cpu";
25			reg = <0>;
26			fsl,portid-mapping = <0x80000000>;
27		};
28		cpu1: PowerPC,e500mc@1 {
29			device_type = "cpu";
30			reg = <1>;
31			fsl,portid-mapping = <0x40000000>;
32		};
33		cpu2: PowerPC,e500mc@2 {
34			device_type = "cpu";
35			reg = <2>;
36			fsl,portid-mapping = <0x20000000>;
37		};
38		cpu3: PowerPC,e500mc@3 {
39			device_type = "cpu";
40			reg = <3>;
41			fsl,portid-mapping = <0x10000000>;
42		};
43	};
44
45	soc: soc@ffe000000 {
46		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
47		reg = <0xf 0xfe000000 0 0x00001000>;
48		#address-cells = <1>;
49		#size-cells = <1>;
50		device_type = "soc";
51		compatible = "simple-bus";
52
53		mpic: pic@40000 {
54			interrupt-controller;
55			#address-cells = <0>;
56			#interrupt-cells = <4>;
57			reg = <0x40000 0x40000>;
58			compatible = "fsl,mpic", "chrp,open-pic";
59			device_type = "open-pic";
60			clock-frequency = <0x0>;
61		};
62
63		espi0: spi@110000 {
64			compatible = "fsl,mpc8536-espi";
65			#address-cells = <1>;
66			#size-cells = <0>;
67			reg = <0x110000 0x1000>;
68			fsl,espi-num-chipselects = <4>;
69			status = "disabled";
70		};
71
72		usb0: usb@210000 {
73			compatible = "fsl-usb2-mph";
74			reg = <0x210000 0x1000>;
75			phy_type = "utmi";
76		};
77
78		usb1: usb@211000 {
79			compatible = "fsl-usb2-mph";
80			reg = <0x210000 0x1000>;
81			phy_type = "utmi";
82		};
83
84		sata: sata@220000 {
85			compatible = "fsl,pq-sata-v2";
86			reg = <0x220000 0x1000>;
87			interrupts = <68 0x2 0 0>;
88			sata-offset = <0x1000>;
89			sata-number = <2>;
90			sata-fpdma = <0>;
91		};
92
93		esdhc: esdhc@114000 {
94			compatible = "fsl,esdhc";
95			reg = <0x114000 0x1000>;
96			clock-frequency = <0>;
97		};
98
99		/include/ "qoriq-i2c-0.dtsi"
100		/include/ "qoriq-i2c-1.dtsi"
101	};
102
103	pcie@ffe200000 {
104		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
105		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
106		law_trgt_if = <0>;
107		#address-cells = <3>;
108		#size-cells = <2>;
109		device_type = "pci";
110		bus-range = <0x0 0xff>;
111		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
112			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
113	};
114
115	pcie@ffe201000 {
116		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
117		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
118		law_trgt_if = <1>;
119		#address-cells = <3>;
120		#size-cells = <2>;
121		device_type = "pci";
122		bus-range = <0x0 0xff>;
123		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
124			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
125	};
126
127	pcie@ffe202000 {
128		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
129		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
130		law_trgt_if = <2>;
131		#address-cells = <3>;
132		#size-cells = <2>;
133		device_type = "pci";
134		bus-range = <0x0 0xff>;
135		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
136			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
137	};
138};
139