1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P4080DS Device Tree Source
4 *
5 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019-2020 NXP
7 */
8
9/include/ "p4080.dtsi"
10
11/ {
12	model = "fsl,P4080DS";
13	compatible = "fsl,P4080DS";
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&mpic>;
17
18	aliases {
19		phy_rgmii = &phyrgmii;
20		phy5_slot3 = &phy5slot3;
21		phy6_slot3 = &phy6slot3;
22		phy7_slot3 = &phy7slot3;
23		phy8_slot3 = &phy8slot3;
24		emi1_slot3 = &p4080mdio2;
25		emi1_slot4 = &p4080mdio1;
26		emi1_slot5 = &p4080mdio3;
27		emi1_rgmii = &p4080mdio0;
28		emi2_slot4 = &p4080xmdio1;
29		emi2_slot5 = &p4080xmdio3;
30		spi0 = &espi0;
31	};
32
33	soc: soc@ffe000000 {
34		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
35		reg = <0xf 0xfe000000 0 0x00001000>;
36
37		fman@400000 {
38			ethernet@e0000 {
39				phy-handle = <&phy0>;
40				phy-connection-type = "sgmii";
41			};
42
43			ethernet@e2000 {
44				phy-handle = <&phy1>;
45				phy-connection-type = "sgmii";
46			};
47
48			ethernet@e4000 {
49				phy-handle = <&phy2>;
50				phy-connection-type = "sgmii";
51			};
52
53			ethernet@e6000 {
54				phy-handle = <&phy3>;
55				phy-connection-type = "sgmii";
56			};
57
58			ethernet@f0000 {
59				phy-handle = <&phy10>;
60				phy-connection-type = "xgmii";
61			};
62		};
63
64		fman@500000 {
65			ethernet@e0000 {
66				phy-handle = <&phy5>;
67				phy-connection-type = "sgmii";
68			};
69
70			ethernet@e2000 {
71				phy-handle = <&phy6>;
72				phy-connection-type = "sgmii";
73			};
74
75			ethernet@e4000 {
76				phy-handle = <&phy7>;
77				phy-connection-type = "sgmii";
78			};
79
80			ethernet@e6000 {
81				phy-handle = <&phy8>;
82				phy-connection-type = "sgmii";
83			};
84
85			ethernet@f0000 {
86				phy-handle = <&phy11>;
87				phy-connection-type = "xgmii";
88			};
89		};
90	};
91
92	mdio-mux-emi1 {
93		#address-cells = <1>;
94		#size-cells = <0>;
95		compatible = "mdio-mux-gpio", "mdio-mux";
96		mdio-parent-bus = <&mdio0>;
97		gpios = <&gpio0 1 0>, <&gpio0 0 0>;
98
99		p4080mdio0: mdio@0 {
100			#address-cells = <1>;
101			#size-cells = <0>;
102			reg = <0>;
103
104			phyrgmii: ethernet-phy@0 {
105				reg = <0x0>;
106			};
107		};
108
109		p4080mdio1: mdio@1 {
110			#address-cells = <1>;
111			#size-cells = <0>;
112			reg = <1>;
113
114			phy5: ethernet-phy@1c {
115				reg = <0x1c>;
116			};
117
118			phy6: ethernet-phy@1d {
119				reg = <0x1d>;
120			};
121
122			phy7: ethernet-phy@1e {
123				reg = <0x1e>;
124			};
125
126			phy8: ethernet-phy@1f {
127				reg = <0x1f>;
128			};
129		};
130
131		p4080mdio2: mdio@2 {
132			#address-cells = <1>;
133			#size-cells = <0>;
134			reg = <2>;
135			status = "disabled";
136
137			phy5slot3: ethernet-phy@1c {
138				reg = <0x1c>;
139			};
140
141			phy6slot3: ethernet-phy@1d {
142				reg = <0x1d>;
143			};
144
145			phy7slot3: ethernet-phy@1e {
146				reg = <0x1e>;
147			};
148
149			phy8slot3: ethernet-phy@1f {
150				reg = <0x1f>;
151			};
152		};
153
154		p4080mdio3: mdio@3 {
155			#address-cells = <1>;
156			#size-cells = <0>;
157			reg = <3>;
158
159			phy0: ethernet-phy@1c {
160				reg = <0x1c>;
161			};
162
163			phy1: ethernet-phy@1d {
164				reg = <0x1d>;
165			};
166
167			phy2: ethernet-phy@1e {
168				reg = <0x1e>;
169			};
170
171			phy3: ethernet-phy@1f {
172				reg = <0x1f>;
173			};
174		};
175	};
176
177	mdio-mux-emi2 {
178		#address-cells = <1>;
179		#size-cells = <0>;
180		compatible = "mdio-mux-gpio", "mdio-mux";
181		mdio-parent-bus = <&xmdio0>;
182		gpios = <&gpio0 3 0>, <&gpio0 2 0>;
183
184		p4080xmdio1: mdio@1 {
185			#address-cells = <1>;
186			#size-cells = <0>;
187			reg = <1>;
188
189			phy11: ethernet-phy@0 {
190				compatible = "ethernet-phy-ieee802.3-c45";
191				reg = <0x0>;
192			};
193		};
194
195		p4080xmdio3: mdio@3 {
196			#address-cells = <1>;
197			#size-cells = <0>;
198			reg = <3>;
199
200			phy10: ethernet-phy@4 {
201				compatible = "ethernet-phy-ieee802.3-c45";
202				reg = <0x4>;
203			};
204		};
205	};
206};
207
208&espi0 {
209	status = "okay";
210	flash@0 {
211		compatible = "jedec,spi-nor";
212		#address-cells = <1>;
213		#size-cells = <1>;
214		reg = <0>;
215		/* input clock */
216		spi-max-frequency = <10000000>;
217	};
218};
219
220/include/ "p4080si-post.dtsi"
221