1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
4 *
5 * Copyright 2011 Freescale Semiconductor Inc.
6 */
7
8mpic: pic@40000 {
9	interrupt-controller;
10	#address-cells = <0>;
11	#interrupt-cells = <4>;
12	reg = <0x40000 0x40000>;
13	compatible = "fsl,mpic", "chrp,open-pic";
14	device_type = "open-pic";
15	clock-frequency = <0x0>;
16};
17
18timer@41100 {
19	compatible = "fsl,mpic-global-timer";
20	reg = <0x41100 0x100 0x41300 4>;
21	interrupts = <0 0 3 0
22		      1 0 3 0
23		      2 0 3 0
24		      3 0 3 0>;
25};
26
27msi0: msi@41600 {
28	compatible = "fsl,mpic-msi";
29	reg = <0x41600 0x200 0x44140 4>;
30	msi-available-ranges = <0 0x100>;
31	interrupts = <
32		0xe0 0 0 0
33		0xe1 0 0 0
34		0xe2 0 0 0
35		0xe3 0 0 0
36		0xe4 0 0 0
37		0xe5 0 0 0
38		0xe6 0 0 0
39		0xe7 0 0 0>;
40};
41
42msi1: msi@41800 {
43	compatible = "fsl,mpic-msi";
44	reg = <0x41800 0x200 0x45140 4>;
45	msi-available-ranges = <0 0x100>;
46	interrupts = <
47		0xe8 0 0 0
48		0xe9 0 0 0
49		0xea 0 0 0
50		0xeb 0 0 0
51		0xec 0 0 0
52		0xed 0 0 0
53		0xee 0 0 0
54		0xef 0 0 0>;
55};
56
57msi2: msi@41a00 {
58	compatible = "fsl,mpic-msi";
59	reg = <0x41a00 0x200 0x46140 4>;
60	msi-available-ranges = <0 0x100>;
61	interrupts = <
62		0xf0 0 0 0
63		0xf1 0 0 0
64		0xf2 0 0 0
65		0xf3 0 0 0
66		0xf4 0 0 0
67		0xf5 0 0 0
68		0xf6 0 0 0
69		0xf7 0 0 0>;
70};
71
72timer@42100 {
73	compatible = "fsl,mpic-global-timer";
74	reg = <0x42100 0x100 0x42300 4>;
75	interrupts = <4 0 3 0
76		      5 0 3 0
77		      6 0 3 0
78		      7 0 3 0>;
79};
80