1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
4 *
5 * Copyright 2013 Freescale Semiconductor Inc.
6 * Copyright 2018,2020 NXP
7 */
8
9/dts-v1/;
10
11/include/ "e6500_power_isa.dtsi"
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&mpic>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: PowerPC,e6500@0 {
23			device_type = "cpu";
24			reg = <0 1>;
25			fsl,portid-mapping = <0x80000000>;
26		};
27		cpu1: PowerPC,e6500@2 {
28			device_type = "cpu";
29			reg = <2 3>;
30			fsl,portid-mapping = <0x80000000>;
31		};
32		cpu2: PowerPC,e6500@4 {
33			device_type = "cpu";
34			reg = <4 5>;
35			fsl,portid-mapping = <0x80000000>;
36		};
37		cpu3: PowerPC,e6500@6 {
38			device_type = "cpu";
39			reg = <6 7>;
40			fsl,portid-mapping = <0x80000000>;
41		};
42	};
43
44	soc: soc@ffe000000 {
45		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
46		reg = <0xf 0xfe000000 0 0x00001000>;
47		#address-cells = <1>;
48		#size-cells = <1>;
49		device_type = "soc";
50		compatible = "simple-bus";
51
52		mpic: pic@40000 {
53			interrupt-controller;
54			#address-cells = <0>;
55			#interrupt-cells = <4>;
56			reg = <0x40000 0x40000>;
57			compatible = "fsl,mpic";
58			device_type = "open-pic";
59			clock-frequency = <0x0>;
60		};
61
62		esdhc: esdhc@114000 {
63			compatible = "fsl,esdhc";
64			reg = <0x114000 0x1000>;
65			interrupts = <48 2 0 0>;
66			clock-frequency = <0>;
67			sdhci,auto-cmd12;
68			bus-width = <4>;
69			voltage-ranges = <1800 1800 3300 3300>;
70		};
71
72		espi0: spi@110000 {
73			#address-cells = <1>;
74			#size-cells = <0>;
75			compatible = "fsl,mpc8536-espi";
76			reg = <0x110000 0x1000>;
77			interrupts = <53 0x2 0 0>;
78			fsl,espi-num-chipselects = <4>;
79			status = "disabled";
80		};
81
82		usb0: usb@210000 {
83			compatible = "fsl-usb2-mph";
84			reg = <0x210000 0x1000>;
85			#address-cells = <1>;
86			#size-cells = <0>;
87			interrupts = <44 0x2 0 0>;
88			phy_type = "utmi";
89		};
90
91		usb1: usb@211000 {
92			compatible = "fsl-usb2-dr";
93			reg = <0x211000 0x1000>;
94			#address-cells = <1>;
95			#size-cells = <0>;
96			interrupts = <45 0x2 0 0>;
97			dr_mode = "host";
98			phy_type = "utmi";
99		};
100
101		sata: sata@220000 {
102			compatible = "fsl,pq-sata-v2";
103			reg = <0x220000 0x1000>;
104			interrupts = <68 0x2 0 0>;
105			sata-offset = <0x1000>;
106			sata-number = <2>;
107			sata-fpdma = <0>;
108		};
109		/include/ "qoriq-i2c-0.dtsi"
110		/include/ "qoriq-i2c-1.dtsi"
111	};
112
113	pcie@ffe240000 {
114		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
115		reg = <0xf 0xfe240000 0x0 0x4000>;   /* registers */
116		law_trgt_if = <0>;
117		#address-cells = <3>;
118		#size-cells = <2>;
119		device_type = "pci";
120		bus-range = <0x0 0xff>;
121		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
122			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
123	};
124
125	pcie@ffe250000 {
126		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
127		reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
128		law_trgt_if = <1>;
129		#address-cells = <3>;
130		#size-cells = <2>;
131		device_type = "pci";
132		bus-range = <0x0 0xff>;
133		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
134			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
135	};
136
137	pcie@ffe260000 {
138		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
139		reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
140		law_trgt_if = <2>;
141		#address-cells = <3>;
142		#size-cells = <2>;
143		device_type = "pci";
144		bus-range = <0x0 0xff>;
145		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
146			  0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
147	};
148
149	pcie@ffe270000 {
150		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
151		reg = <0xf 0xfe270000 0x0 0x1000>;   /* registers */
152		law_trgt_if = <3>;
153		#address-cells = <3>;
154		#size-cells = <2>;
155		device_type = "pci";
156		bus-range = <0x0 0xff>;
157		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
158			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */
159	};
160};
161