1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
4 * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
7 */
8
9#include <config.h>
10#include <ppc_asm.tmpl>
11#include <ppc_defs.h>
12
13#include <asm/cache.h>
14
15/*------------------------------------------------------------------------------- */
16/* Function:	 ppcDcbf */
17/* Description:	 Data Cache block flush */
18/* Input:	 r3 = effective address */
19/* Output:	 none. */
20/*------------------------------------------------------------------------------- */
21	.globl	ppcDcbf
22ppcDcbf:
23	dcbf	r0,r3
24	blr
25
26/*------------------------------------------------------------------------------- */
27/* Function:	 ppcDcbi */
28/* Description:	 Data Cache block Invalidate */
29/* Input:	 r3 = effective address */
30/* Output:	 none. */
31/*------------------------------------------------------------------------------- */
32	.globl	ppcDcbi
33ppcDcbi:
34	dcbi	r0,r3
35	blr
36
37/*--------------------------------------------------------------------------
38 * Function:	 ppcDcbz
39 * Description:	 Data Cache block zero.
40 * Input:	 r3 = effective address
41 * Output:	 none.
42 *-------------------------------------------------------------------------- */
43
44	.globl	ppcDcbz
45ppcDcbz:
46	dcbz	r0,r3
47	blr
48
49/*------------------------------------------------------------------------------- */
50/* Function:	 ppcSync */
51/* Description:	 Processor Synchronize */
52/* Input:	 none. */
53/* Output:	 none. */
54/*------------------------------------------------------------------------------- */
55	.globl	ppcSync
56ppcSync:
57	sync
58	blr
59
60/*
61 * Write any modified data cache blocks out to memory and invalidate them.
62 * Does not invalidate the corresponding instruction cache blocks.
63 *
64 * flush_dcache_range(unsigned long start, unsigned long stop)
65 */
66_GLOBAL(flush_dcache_range)
67#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
68	li	r5,L1_CACHE_BYTES-1
69	andc	r3,r3,r5
70	subf	r4,r3,r4
71	add	r4,r4,r5
72	srwi.	r4,r4,L1_CACHE_SHIFT
73	beqlr
74	mtctr	r4
75
761:	dcbf	0,r3
77	addi	r3,r3,L1_CACHE_BYTES
78	bdnz	1b
79	sync				/* wait for dcbst's to get to ram */
80#endif
81	blr
82
83/*
84 * Like above, but invalidate the D-cache.  This is used by the 8xx
85 * to invalidate the cache so the PPC core doesn't get stale data
86 * from the CPM (no cache snooping here :-).
87 *
88 * invalidate_dcache_range(unsigned long start, unsigned long stop)
89 */
90_GLOBAL(invalidate_dcache_range)
91#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
92	li	r5,L1_CACHE_BYTES-1
93	andc	r3,r3,r5
94	subf	r4,r3,r4
95	add	r4,r4,r5
96	srwi.	r4,r4,L1_CACHE_SHIFT
97	beqlr
98	mtctr	r4
99
100	sync
1011:	dcbi	0,r3
102	addi	r3,r3,L1_CACHE_BYTES
103	bdnz	1b
104	sync				/* wait for dcbi's to get to ram */
105#endif
106	blr
107
108