1menu "RISC-V architecture"
2	depends on RISCV
3
4config SYS_ARCH
5	default "riscv"
6
7choice
8	prompt "Target select"
9	optional
10
11config TARGET_AX25_AE350
12	bool "Support ax25-ae350"
13
14config TARGET_MICROCHIP_ICICLE
15	bool "Support Microchip PolarFire-SoC Icicle Board"
16
17config TARGET_QEMU_VIRT
18	bool "Support QEMU Virt Board"
19
20config TARGET_SIFIVE_FU540
21	bool "Support SiFive FU540 Board"
22
23config TARGET_SIPEED_MAIX
24	bool "Support Sipeed Maix Board"
25
26endchoice
27
28config SYS_ICACHE_OFF
29	bool "Do not enable icache"
30	default n
31	help
32	  Do not enable instruction cache in U-Boot.
33
34config SPL_SYS_ICACHE_OFF
35	bool "Do not enable icache in SPL"
36	depends on SPL
37	default SYS_ICACHE_OFF
38	help
39	  Do not enable instruction cache in SPL.
40
41config SYS_DCACHE_OFF
42	bool "Do not enable dcache"
43	default n
44	help
45	  Do not enable data cache in U-Boot.
46
47config SPL_SYS_DCACHE_OFF
48	bool "Do not enable dcache in SPL"
49	depends on SPL
50	default SYS_DCACHE_OFF
51	help
52	  Do not enable data cache in SPL.
53
54# board-specific options below
55source "board/AndesTech/ax25-ae350/Kconfig"
56source "board/emulation/qemu-riscv/Kconfig"
57source "board/microchip/mpfs_icicle/Kconfig"
58source "board/sifive/fu540/Kconfig"
59source "board/sipeed/maix/Kconfig"
60
61# platform-specific options below
62source "arch/riscv/cpu/ax25/Kconfig"
63source "arch/riscv/cpu/fu540/Kconfig"
64source "arch/riscv/cpu/generic/Kconfig"
65
66# architecture-specific options below
67
68choice
69	prompt "Base ISA"
70	default ARCH_RV32I
71
72config ARCH_RV32I
73	bool "RV32I"
74	select 32BIT
75	help
76	  Choose this option to target the RV32I base integer instruction set.
77
78config ARCH_RV64I
79	bool "RV64I"
80	select 64BIT
81	select PHYS_64BIT
82	help
83	  Choose this option to target the RV64I base integer instruction set.
84
85endchoice
86
87choice
88	prompt "Code Model"
89	default CMODEL_MEDLOW
90
91config CMODEL_MEDLOW
92	bool "medium low code model"
93	help
94	  U-Boot and its statically defined symbols must lie within a single 2 GiB
95	  address range and must lie between absolute addresses -2 GiB and +2 GiB.
96
97config CMODEL_MEDANY
98	bool "medium any code model"
99	help
100	  U-Boot and its statically defined symbols must be within any single 2 GiB
101	  address range.
102
103endchoice
104
105choice
106	prompt "Run Mode"
107	default RISCV_MMODE
108
109config RISCV_MMODE
110	bool "Machine"
111	help
112	  Choose this option to build U-Boot for RISC-V M-Mode.
113
114config RISCV_SMODE
115	bool "Supervisor"
116	help
117	  Choose this option to build U-Boot for RISC-V S-Mode.
118
119endchoice
120
121choice
122	prompt "SPL Run Mode"
123	default SPL_RISCV_MMODE
124	depends on SPL
125
126config SPL_RISCV_MMODE
127	bool "Machine"
128	help
129	  Choose this option to build U-Boot SPL for RISC-V M-Mode.
130
131config SPL_RISCV_SMODE
132	bool "Supervisor"
133	help
134	  Choose this option to build U-Boot SPL for RISC-V S-Mode.
135
136endchoice
137
138config RISCV_ISA_C
139	bool "Emit compressed instructions"
140	default y
141	help
142	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
143	  when building U-Boot, which results in compressed instructions in the
144	  U-Boot binary.
145
146config RISCV_ISA_A
147	def_bool y
148
149config 32BIT
150	bool
151
152config 64BIT
153	bool
154
155config DMA_ADDR_T_64BIT
156	bool
157	default y if 64BIT
158
159config SIFIVE_CLINT
160	bool
161	depends on RISCV_MMODE || SPL_RISCV_MMODE
162	help
163	  The SiFive CLINT block holds memory-mapped control and status registers
164	  associated with software and timer interrupts.
165
166config ANDES_PLIC
167	bool
168	depends on RISCV_MMODE || SPL_RISCV_MMODE
169	select REGMAP
170	select SYSCON
171	select SPL_REGMAP if SPL
172	select SPL_SYSCON if SPL
173	help
174	  The Andes PLIC block holds memory-mapped claim and pending registers
175	  associated with software interrupt.
176
177config SYS_MALLOC_F_LEN
178	default 0x1000
179
180config SMP
181	bool "Symmetric Multi-Processing"
182	depends on SBI_V01 || !RISCV_SMODE
183	help
184	  This enables support for systems with more than one CPU. If
185	  you say N here, U-Boot will run on single and multiprocessor
186	  machines, but will use only one CPU of a multiprocessor
187	  machine. If you say Y here, U-Boot will run on many, but not
188	  all, single processor machines.
189
190config SPL_SMP
191	bool "Symmetric Multi-Processing in SPL"
192	depends on SPL && SPL_RISCV_MMODE
193	default y
194	help
195	  This enables support for systems with more than one CPU in SPL.
196	  If you say N here, U-Boot SPL will run on single and multiprocessor
197	  machines, but will use only one CPU of a multiprocessor
198	  machine. If you say Y here, U-Boot SPL will run on many, but not
199	  all, single processor machines.
200
201config NR_CPUS
202	int "Maximum number of CPUs (2-32)"
203	range 2 32
204	depends on SMP || SPL_SMP
205	default 8
206	help
207	  On multiprocessor machines, U-Boot sets up a stack for each CPU.
208	  Stack memory is pre-allocated. U-Boot must therefore know the
209	  maximum number of CPUs that may be present.
210
211config SBI
212	bool
213	default y if RISCV_SMODE || SPL_RISCV_SMODE
214
215choice
216	prompt "SBI support"
217	default SBI_V02
218
219config SBI_V01
220	bool "SBI v0.1 support"
221	depends on SBI
222	help
223	  This config allows kernel to use SBI v0.1 APIs. This will be
224	  deprecated in future once legacy M-mode software are no longer in use.
225
226config SBI_V02
227	bool "SBI v0.2 support"
228	depends on SBI
229	help
230	  This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
231	  scalable and extendable to handle future needs for RISC-V supervisor
232	  interfaces. For example, with SBI v0.2 HSM extension, only a single
233	  hart need to boot and enter operating system. The booting hart can
234	  bring up secondary harts one by one afterwards.
235
236	  Choose this option if OpenSBI v0.7 or above release is used together
237	  with U-Boot.
238
239endchoice
240
241config SBI_IPI
242	bool
243	depends on SBI
244	default y if RISCV_SMODE || SPL_RISCV_SMODE
245	depends on SMP
246
247config XIP
248	bool "XIP mode"
249	help
250	  XIP (eXecute In Place) is a method for executing code directly
251	  from a NOR flash memory without copying the code to ram.
252	  Say yes here if U-Boot boots from flash directly.
253
254config SHOW_REGS
255	bool "Show registers on unhandled exception"
256
257config RISCV_PRIV_1_9
258	bool "Use version 1.9 of the RISC-V priviledged specification"
259	help
260	  Older versions of the RISC-V priviledged specification had
261	  separate counter enable CSRs for each privilege mode. Writing
262	  to the unified mcounteren CSR on a processor implementing the
263	  old specification will result in an illegal instruction
264	  exception. In addition to counter CSR changes, the way virtual
265	  memory is configured was also changed.
266
267config STACK_SIZE_SHIFT
268	int
269	default 14
270
271config OF_BOARD_FIXUP
272	default y if OF_SEPARATE && RISCV_SMODE
273
274endmenu
275