1/dts-v1/; 2 3/ { 4 #address-cells = <1>; 5 #size-cells = <1>; 6 compatible = "andestech,a25"; 7 model = "andestech,a25"; 8 9 aliases { 10 uart0 = &serial0; 11 spi0 = &spi; 12 }; 13 14 chosen { 15 bootargs = "console=ttyS0,38400n8 debug loglevel=7"; 16 stdout-path = "uart0:38400n8"; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 timebase-frequency = <60000000>; 23 CPU0: cpu@0 { 24 device_type = "cpu"; 25 reg = <0>; 26 status = "okay"; 27 compatible = "riscv"; 28 riscv,isa = "rv32imafdc"; 29 riscv,priv-major = <1>; 30 riscv,priv-minor = <10>; 31 mmu-type = "riscv,sv32"; 32 clock-frequency = <60000000>; 33 i-cache-size = <0x8000>; 34 i-cache-line-size = <32>; 35 d-cache-size = <0x8000>; 36 d-cache-line-size = <32>; 37 next-level-cache = <&L2>; 38 CPU0_intc: interrupt-controller { 39 #interrupt-cells = <1>; 40 interrupt-controller; 41 compatible = "riscv,cpu-intc"; 42 }; 43 }; 44 CPU1: cpu@1 { 45 device_type = "cpu"; 46 reg = <1>; 47 status = "okay"; 48 compatible = "riscv"; 49 riscv,isa = "rv32imafdc"; 50 riscv,priv-major = <1>; 51 riscv,priv-minor = <10>; 52 mmu-type = "riscv,sv32"; 53 clock-frequency = <60000000>; 54 i-cache-size = <0x8000>; 55 i-cache-line-size = <32>; 56 d-cache-size = <0x8000>; 57 d-cache-line-size = <32>; 58 next-level-cache = <&L2>; 59 CPU1_intc: interrupt-controller { 60 #interrupt-cells = <1>; 61 interrupt-controller; 62 compatible = "riscv,cpu-intc"; 63 }; 64 }; 65 CPU2: cpu@2 { 66 device_type = "cpu"; 67 reg = <2>; 68 status = "okay"; 69 compatible = "riscv"; 70 riscv,isa = "rv32imafdc"; 71 riscv,priv-major = <1>; 72 riscv,priv-minor = <10>; 73 mmu-type = "riscv,sv32"; 74 clock-frequency = <60000000>; 75 i-cache-size = <0x8000>; 76 i-cache-line-size = <32>; 77 d-cache-size = <0x8000>; 78 d-cache-line-size = <32>; 79 next-level-cache = <&L2>; 80 CPU2_intc: interrupt-controller { 81 #interrupt-cells = <1>; 82 interrupt-controller; 83 compatible = "riscv,cpu-intc"; 84 }; 85 }; 86 CPU3: cpu@3 { 87 device_type = "cpu"; 88 reg = <3>; 89 status = "okay"; 90 compatible = "riscv"; 91 riscv,isa = "rv32imafdc"; 92 riscv,priv-major = <1>; 93 riscv,priv-minor = <10>; 94 mmu-type = "riscv,sv32"; 95 clock-frequency = <60000000>; 96 i-cache-size = <0x8000>; 97 i-cache-line-size = <32>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <32>; 100 next-level-cache = <&L2>; 101 CPU3_intc: interrupt-controller { 102 #interrupt-cells = <1>; 103 interrupt-controller; 104 compatible = "riscv,cpu-intc"; 105 }; 106 }; 107 }; 108 109 L2: l2-cache@e0500000 { 110 compatible = "v5l2cache"; 111 cache-level = <2>; 112 cache-size = <0x40000>; 113 reg = <0xe0500000 0x40000>; 114 andes,inst-prefetch = <3>; 115 andes,data-prefetch = <3>; 116 /* The value format is <XRAMOCTL XRAMICTL> */ 117 andes,tag-ram-ctl = <0 0>; 118 andes,data-ram-ctl = <0 0>; 119 }; 120 121 memory@0 { 122 device_type = "memory"; 123 reg = <0x00000000 0x40000000>; 124 }; 125 126 soc { 127 #address-cells = <1>; 128 #size-cells = <1>; 129 compatible = "simple-bus"; 130 ranges; 131 132 plic0: interrupt-controller@e4000000 { 133 compatible = "riscv,plic0"; 134 #address-cells = <1>; 135 #interrupt-cells = <1>; 136 interrupt-controller; 137 reg = <0xe4000000 0x2000000>; 138 riscv,ndev=<71>; 139 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 140 &CPU1_intc 11 &CPU1_intc 9 141 &CPU2_intc 11 &CPU2_intc 9 142 &CPU3_intc 11 &CPU3_intc 9>; 143 }; 144 145 plic1: interrupt-controller@e6400000 { 146 compatible = "riscv,plic1"; 147 #address-cells = <1>; 148 #interrupt-cells = <1>; 149 interrupt-controller; 150 reg = <0xe6400000 0x400000>; 151 riscv,ndev=<2>; 152 interrupts-extended = <&CPU0_intc 3 153 &CPU1_intc 3 154 &CPU2_intc 3 155 &CPU3_intc 3>; 156 }; 157 158 plmt0@e6000000 { 159 compatible = "riscv,plmt0"; 160 interrupts-extended = <&CPU0_intc 7 161 &CPU1_intc 7 162 &CPU2_intc 7 163 &CPU3_intc 7>; 164 reg = <0xe6000000 0x100000>; 165 }; 166 }; 167 168 spiclk: virt_100mhz { 169 #clock-cells = <0>; 170 compatible = "fixed-clock"; 171 clock-frequency = <100000000>; 172 }; 173 174 timer0: timer@f0400000 { 175 compatible = "andestech,atcpit100"; 176 reg = <0xf0400000 0x1000>; 177 clock-frequency = <60000000>; 178 interrupts = <3 4>; 179 interrupt-parent = <&plic0>; 180 }; 181 182 serial0: serial@f0300000 { 183 compatible = "andestech,uart16550", "ns16550a"; 184 reg = <0xf0300000 0x1000>; 185 interrupts = <9 4>; 186 clock-frequency = <19660800>; 187 reg-shift = <2>; 188 reg-offset = <32>; 189 no-loopback-test = <1>; 190 interrupt-parent = <&plic0>; 191 }; 192 193 mac0: mac@e0100000 { 194 compatible = "andestech,atmac100"; 195 reg = <0xe0100000 0x1000>; 196 interrupts = <19 4>; 197 interrupt-parent = <&plic0>; 198 }; 199 200 mmc0: mmc@f0e00000 { 201 compatible = "andestech,atfsdc010"; 202 max-frequency = <100000000>; 203 clock-freq-min-max = <400000 100000000>; 204 fifo-depth = <0x10>; 205 reg = <0xf0e00000 0x1000>; 206 interrupts = <18 4>; 207 cap-sd-highspeed; 208 interrupt-parent = <&plic0>; 209 }; 210 211 dma0: dma@f0c00000 { 212 compatible = "andestech,atcdmac300"; 213 reg = <0xf0c00000 0x1000>; 214 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; 215 dma-channels = <8>; 216 interrupt-parent = <&plic0>; 217 }; 218 219 lcd0: lcd@e0200000 { 220 compatible = "andestech,atflcdc100"; 221 reg = <0xe0200000 0x1000>; 222 interrupts = <20 4>; 223 interrupt-parent = <&plic0>; 224 }; 225 226 smc0: smc@e0400000 { 227 compatible = "andestech,atfsmc020"; 228 reg = <0xe0400000 0x1000>; 229 }; 230 231 snd0: snd@f0d00000 { 232 compatible = "andestech,atfac97"; 233 reg = <0xf0d00000 0x1000>; 234 interrupts = <17 4>; 235 interrupt-parent = <&plic0>; 236 }; 237 238 pmu { 239 compatible = "riscv,base-pmu"; 240 }; 241 242 virtio_mmio@fe007000 { 243 interrupts = <0x17 0x4>; 244 interrupt-parent = <0x2>; 245 reg = <0xfe007000 0x1000>; 246 compatible = "virtio,mmio"; 247 }; 248 249 virtio_mmio@fe006000 { 250 interrupts = <0x16 0x4>; 251 interrupt-parent = <0x2>; 252 reg = <0xfe006000 0x1000>; 253 compatible = "virtio,mmio"; 254 }; 255 256 virtio_mmio@fe005000 { 257 interrupts = <0x15 0x4>; 258 interrupt-parent = <0x2>; 259 reg = <0xfe005000 0x1000>; 260 compatible = "virtio,mmio"; 261 }; 262 263 virtio_mmio@fe004000 { 264 interrupts = <0x14 0x4>; 265 interrupt-parent = <0x2>; 266 reg = <0xfe004000 0x1000>; 267 compatible = "virtio,mmio"; 268 }; 269 270 virtio_mmio@fe003000 { 271 interrupts = <0x13 0x4>; 272 interrupt-parent = <0x2>; 273 reg = <0xfe003000 0x1000>; 274 compatible = "virtio,mmio"; 275 }; 276 277 virtio_mmio@fe002000 { 278 interrupts = <0x12 0x4>; 279 interrupt-parent = <0x2>; 280 reg = <0xfe002000 0x1000>; 281 compatible = "virtio,mmio"; 282 }; 283 284 virtio_mmio@fe001000 { 285 interrupts = <0x11 0x4>; 286 interrupt-parent = <0x2>; 287 reg = <0xfe001000 0x1000>; 288 compatible = "virtio,mmio"; 289 }; 290 291 virtio_mmio@fe000000 { 292 interrupts = <0x10 0x4>; 293 interrupt-parent = <0x2>; 294 reg = <0xfe000000 0x1000>; 295 compatible = "virtio,mmio"; 296 }; 297 298 nor@0,0 { 299 #address-cells = <1>; 300 #size-cells = <1>; 301 compatible = "cfi-flash"; 302 reg = <0x88000000 0x4000000>; 303 bank-width = <2>; 304 device-width = <1>; 305 }; 306 307 spi: spi@f0b00000 { 308 compatible = "andestech,atcspi200"; 309 reg = <0xf0b00000 0x1000>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 num-cs = <1>; 313 clocks = <&spiclk>; 314 interrupts = <4 4>; 315 interrupt-parent = <&plic0>; 316 flash@0 { 317 compatible = "jedec,spi-nor"; 318 spi-max-frequency = <50000000>; 319 reg = <0>; 320 spi-cpol; 321 spi-cpha; 322 }; 323 }; 324}; 325