1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 Google, LLC
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
7 #define LOG_CATEGORY UCLASS_IRQ
8
9 #include <common.h>
10 #include <dm.h>
11 #include <irq.h>
12 #include <log.h>
13 #include <acpi/acpi_device.h>
14 #include <asm/io.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/x86-irq.h>
17
18 /**
19 * struct acpi_gpe_priv - private driver information
20 *
21 * @acpi_base: Base I/O address of ACPI registers
22 */
23 struct acpi_gpe_priv {
24 ulong acpi_base;
25 };
26
27 #define GPE0_STS(x) (0x20 + ((x) * 4))
28
acpi_gpe_read_and_clear(struct irq * irq)29 static int acpi_gpe_read_and_clear(struct irq *irq)
30 {
31 struct acpi_gpe_priv *priv = dev_get_priv(irq->dev);
32 u32 mask, sts;
33 ulong start;
34 int ret = 0;
35 int bank;
36
37 bank = irq->id / 32;
38 mask = 1 << (irq->id % 32);
39
40 /* Wait up to 1ms for GPE status to clear */
41 start = get_timer(0);
42 do {
43 if (get_timer(start) > 1)
44 return ret;
45
46 sts = inl(priv->acpi_base + GPE0_STS(bank));
47 if (sts & mask) {
48 outl(mask, priv->acpi_base + GPE0_STS(bank));
49 ret = 1;
50 }
51 } while (sts & mask);
52
53 return ret;
54 }
55
acpi_gpe_of_to_plat(struct udevice * dev)56 static int acpi_gpe_of_to_plat(struct udevice *dev)
57 {
58 struct acpi_gpe_priv *priv = dev_get_priv(dev);
59
60 priv->acpi_base = dev_read_addr(dev);
61 if (!priv->acpi_base || priv->acpi_base == FDT_ADDR_T_NONE)
62 return log_msg_ret("acpi_base", -EINVAL);
63
64 return 0;
65 }
66
acpi_gpe_of_xlate(struct irq * irq,struct ofnode_phandle_args * args)67 static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
68 {
69 irq->id = args->args[0];
70 irq->flags = args->args[1];
71
72 return 0;
73 }
74
75 #if CONFIG_IS_ENABLED(ACPIGEN)
acpi_gpe_get_acpi(const struct irq * irq,struct acpi_irq * acpi_irq)76 static int acpi_gpe_get_acpi(const struct irq *irq, struct acpi_irq *acpi_irq)
77 {
78 memset(acpi_irq, '\0', sizeof(*acpi_irq));
79 acpi_irq->pin = irq->id;
80 acpi_irq->mode = irq->flags & IRQ_TYPE_EDGE_BOTH ?
81 ACPI_IRQ_EDGE_TRIGGERED : ACPI_IRQ_LEVEL_TRIGGERED;
82 acpi_irq->polarity = irq->flags &
83 (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW) ?
84 ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH;
85 acpi_irq->shared = irq->flags & X86_IRQ_TYPE_SHARED ?
86 ACPI_IRQ_SHARED : ACPI_IRQ_EXCLUSIVE;
87 acpi_irq->wake = irq->flags & X86_IRQ_TYPE_WAKE ? ACPI_IRQ_WAKE :
88 ACPI_IRQ_NO_WAKE;
89
90 return 0;
91 }
92 #endif
93
94 static const struct irq_ops acpi_gpe_ops = {
95 .read_and_clear = acpi_gpe_read_and_clear,
96 .of_xlate = acpi_gpe_of_xlate,
97 #if CONFIG_IS_ENABLED(ACPIGEN)
98 .get_acpi = acpi_gpe_get_acpi,
99 #endif
100 };
101
102 static const struct udevice_id acpi_gpe_ids[] = {
103 { .compatible = "intel,acpi-gpe", .data = X86_IRQT_ACPI_GPE },
104 { }
105 };
106
107 U_BOOT_DRIVER(intel_acpi_gpe) = {
108 .name = "intel_acpi_gpe",
109 .id = UCLASS_IRQ,
110 .of_match = acpi_gpe_ids,
111 .ops = &acpi_gpe_ops,
112 .of_to_plat = acpi_gpe_of_to_plat,
113 .priv_auto = sizeof(struct acpi_gpe_priv),
114 };
115