1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <log.h>
10 #include <asm/arch/iomap.h>
11 #include <asm/arch/fsp_bindings.h>
12 #include <asm/fsp2/fsp_internal.h>
13 #include <dm/uclass-internal.h>
14
fspm_update_config(struct udevice * dev,struct fspm_upd * upd)15 int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
16 {
17 struct fsp_m_config *cfg = &upd->config;
18 struct fspm_arch_upd *arch = &upd->arch;
19 int cache_ret = 0;
20 ofnode node;
21 int ret;
22
23 arch->nvs_buffer_ptr = NULL;
24 cache_ret = prepare_mrc_cache(upd);
25 if (cache_ret && cache_ret != -ENOENT)
26 return log_msg_ret("mrc", cache_ret);
27 arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE -
28 arch->stack_size);
29 arch->boot_loader_tolum_size = 0;
30 arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
31 FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
32
33 node = dev_ofnode(dev);
34 if (!ofnode_valid(node))
35 return log_msg_ret("node", -ENOENT);
36 node = ofnode_find_subnode(node, "fsp-m");
37 if (!ofnode_valid(node))
38 return log_msg_ret("fspm", -ENOENT);
39
40 ret = fsp_m_update_config_from_dtb(node, cfg);
41 if (ret)
42 return log_msg_ret("dtb", cache_ret);
43
44 return cache_ret;
45 }
46
47 /*
48 * The FSP-M binary appears to break the SPI controller. It can be fixed by
49 * writing the BAR again, so do that here
50 */
fspm_done(struct udevice * dev)51 int fspm_done(struct udevice *dev)
52 {
53 struct udevice *spi;
54 int ret;
55
56 /* Don't probe the device, since that reads the BAR */
57 ret = uclass_find_first_device(UCLASS_SPI, &spi);
58 if (ret)
59 return log_msg_ret("SPI", ret);
60 if (!spi)
61 return log_msg_ret("no SPI", -ENODEV);
62
63 dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
64 IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);
65
66 return 0;
67 }
68