1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 Google, Inc
4 *
5 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <cpu.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/cpu.h>
14 #include <asm/cpu_x86.h>
15 #include <asm/cpu_common.h>
16 #include <asm/global_data.h>
17 #include <asm/intel_regs.h>
18 #include <asm/msr.h>
19 #include <asm/post.h>
20 #include <asm/turbo.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/pch.h>
23 #include <asm/arch/rcb.h>
24 #include <linux/delay.h>
25
26 struct cpu_broadwell_priv {
27 bool ht_disabled;
28 };
29
30 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
31 static const u8 power_limit_time_sec_to_msr[] = {
32 [0] = 0x00,
33 [1] = 0x0a,
34 [2] = 0x0b,
35 [3] = 0x4b,
36 [4] = 0x0c,
37 [5] = 0x2c,
38 [6] = 0x4c,
39 [7] = 0x6c,
40 [8] = 0x0d,
41 [10] = 0x2d,
42 [12] = 0x4d,
43 [14] = 0x6d,
44 [16] = 0x0e,
45 [20] = 0x2e,
46 [24] = 0x4e,
47 [28] = 0x6e,
48 [32] = 0x0f,
49 [40] = 0x2f,
50 [48] = 0x4f,
51 [56] = 0x6f,
52 [64] = 0x10,
53 [80] = 0x30,
54 [96] = 0x50,
55 [112] = 0x70,
56 [128] = 0x11,
57 };
58
59 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
60 static const u8 power_limit_time_msr_to_sec[] = {
61 [0x00] = 0,
62 [0x0a] = 1,
63 [0x0b] = 2,
64 [0x4b] = 3,
65 [0x0c] = 4,
66 [0x2c] = 5,
67 [0x4c] = 6,
68 [0x6c] = 7,
69 [0x0d] = 8,
70 [0x2d] = 10,
71 [0x4d] = 12,
72 [0x6d] = 14,
73 [0x0e] = 16,
74 [0x2e] = 20,
75 [0x4e] = 24,
76 [0x6e] = 28,
77 [0x0f] = 32,
78 [0x2f] = 40,
79 [0x4f] = 48,
80 [0x6f] = 56,
81 [0x10] = 64,
82 [0x30] = 80,
83 [0x50] = 96,
84 [0x70] = 112,
85 [0x11] = 128,
86 };
87
88 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
arch_cpu_init(void)89 int arch_cpu_init(void)
90 {
91 return 0;
92 }
93 #endif
94
95 /*
96 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
97 * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
98 * when a core is woken up
99 */
pcode_ready(void)100 static int pcode_ready(void)
101 {
102 int wait_count;
103 const int delay_step = 10;
104
105 wait_count = 0;
106 do {
107 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
108 MAILBOX_RUN_BUSY))
109 return 0;
110 wait_count += delay_step;
111 udelay(delay_step);
112 } while (wait_count < 1000);
113
114 return -ETIMEDOUT;
115 }
116
pcode_mailbox_read(u32 command)117 static u32 pcode_mailbox_read(u32 command)
118 {
119 int ret;
120
121 ret = pcode_ready();
122 if (ret) {
123 debug("PCODE: mailbox timeout on wait ready\n");
124 return ret;
125 }
126
127 /* Send command and start transaction */
128 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
129
130 ret = pcode_ready();
131 if (ret) {
132 debug("PCODE: mailbox timeout on completion\n");
133 return ret;
134 }
135
136 /* Read mailbox */
137 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
138 }
139
pcode_mailbox_write(u32 command,u32 data)140 static int pcode_mailbox_write(u32 command, u32 data)
141 {
142 int ret;
143
144 ret = pcode_ready();
145 if (ret) {
146 debug("PCODE: mailbox timeout on wait ready\n");
147 return ret;
148 }
149
150 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
151
152 /* Send command and start transaction */
153 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
154
155 ret = pcode_ready();
156 if (ret) {
157 debug("PCODE: mailbox timeout on completion\n");
158 return ret;
159 }
160
161 return 0;
162 }
163
164 /* @dev is the CPU device */
initialize_vr_config(struct udevice * dev)165 static void initialize_vr_config(struct udevice *dev)
166 {
167 int ramp, min_vid;
168 msr_t msr;
169
170 debug("Initializing VR config\n");
171
172 /* Configure VR_CURRENT_CONFIG */
173 msr = msr_read(MSR_VR_CURRENT_CONFIG);
174 /*
175 * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
176 * on ULT systems
177 */
178 msr.hi &= 0xc0000000;
179 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
180 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
181 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
182 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
183 /* Leave the max instantaneous current limit (12:0) to default */
184 msr_write(MSR_VR_CURRENT_CONFIG, msr);
185
186 /* Configure VR_MISC_CONFIG MSR */
187 msr = msr_read(MSR_VR_MISC_CONFIG);
188 /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
189 msr.hi &= ~(0x3ff << (40 - 32));
190 msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
191 /* Set IOUT_OFFSET to 0 */
192 msr.hi &= ~0xff;
193 /* Set entry ramp rate to slow */
194 msr.hi &= ~(1 << (51 - 32));
195 /* Enable decay mode on C-state entry */
196 msr.hi |= (1 << (52 - 32));
197 /* Set the slow ramp rate */
198 msr.hi &= ~(0x3 << (53 - 32));
199 /* Configure the C-state exit ramp rate */
200 ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
201 "intel,slow-ramp", -1);
202 if (ramp != -1) {
203 /* Configured slow ramp rate */
204 msr.hi |= ((ramp & 0x3) << (53 - 32));
205 /* Set exit ramp rate to slow */
206 msr.hi &= ~(1 << (50 - 32));
207 } else {
208 /* Fast ramp rate / 4 */
209 msr.hi |= (0x01 << (53 - 32));
210 /* Set exit ramp rate to fast */
211 msr.hi |= (1 << (50 - 32));
212 }
213 /* Set MIN_VID (31:24) to allow CPU to have full control */
214 msr.lo &= ~0xff000000;
215 min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
216 "intel,min-vid", 0);
217 msr.lo |= (min_vid & 0xff) << 24;
218 msr_write(MSR_VR_MISC_CONFIG, msr);
219
220 /* Configure VR_MISC_CONFIG2 MSR */
221 msr = msr_read(MSR_VR_MISC_CONFIG2);
222 msr.lo &= ~0xffff;
223 /*
224 * Allow CPU to control minimum voltage completely (15:8) and
225 * set the fast ramp voltage in 10mV steps
226 */
227 if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
228 msr.lo |= 0x006a; /* 1.56V */
229 else
230 msr.lo |= 0x006f; /* 1.60V */
231 msr_write(MSR_VR_MISC_CONFIG2, msr);
232
233 /* Set C9/C10 VCC Min */
234 pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
235 }
236
calibrate_24mhz_bclk(void)237 static int calibrate_24mhz_bclk(void)
238 {
239 int err_code;
240 int ret;
241
242 ret = pcode_ready();
243 if (ret)
244 return ret;
245
246 /* A non-zero value initiates the PCODE calibration */
247 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
248 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
249 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
250
251 ret = pcode_ready();
252 if (ret)
253 return ret;
254
255 err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
256
257 debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
258
259 /* Read the calibrated value */
260 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
261 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
262
263 ret = pcode_ready();
264 if (ret)
265 return ret;
266
267 debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
268 readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
269
270 return 0;
271 }
272
configure_pch_power_sharing(void)273 static void configure_pch_power_sharing(void)
274 {
275 u32 pch_power, pch_power_ext, pmsync, pmsync2;
276 int i;
277
278 /* Read PCH Power levels from PCODE */
279 pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
280 pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
281
282 debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
283 pch_power_ext);
284
285 pmsync = readl(RCB_REG(PMSYNC_CONFIG));
286 pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
287
288 /*
289 * Program PMSYNC_TPR_CONFIG PCH power limit values
290 * pmsync[0:4] = mailbox[0:5]
291 * pmsync[8:12] = mailbox[6:11]
292 * pmsync[16:20] = mailbox[12:17]
293 */
294 for (i = 0; i < 3; i++) {
295 u32 level = pch_power & 0x3f;
296
297 pch_power >>= 6;
298 pmsync &= ~(0x1f << (i * 8));
299 pmsync |= (level & 0x1f) << (i * 8);
300 }
301 writel(pmsync, RCB_REG(PMSYNC_CONFIG));
302
303 /*
304 * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
305 * pmsync2[0:4] = mailbox[23:18]
306 * pmsync2[8:12] = mailbox_ext[6:11]
307 * pmsync2[16:20] = mailbox_ext[12:17]
308 * pmsync2[24:28] = mailbox_ext[18:22]
309 */
310 pmsync2 &= ~0x1f;
311 pmsync2 |= pch_power & 0x1f;
312
313 for (i = 1; i < 4; i++) {
314 u32 level = pch_power_ext & 0x3f;
315
316 pch_power_ext >>= 6;
317 pmsync2 &= ~(0x1f << (i * 8));
318 pmsync2 |= (level & 0x1f) << (i * 8);
319 }
320 writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
321 }
322
bsp_init_before_ap_bringup(struct udevice * dev)323 static int bsp_init_before_ap_bringup(struct udevice *dev)
324 {
325 int ret;
326
327 initialize_vr_config(dev);
328 ret = calibrate_24mhz_bclk();
329 if (ret)
330 return ret;
331 configure_pch_power_sharing();
332
333 return 0;
334 }
335
set_max_ratio(void)336 static void set_max_ratio(void)
337 {
338 msr_t msr, perf_ctl;
339
340 perf_ctl.hi = 0;
341
342 /* Check for configurable TDP option */
343 if (turbo_get_state() == TURBO_ENABLED) {
344 msr = msr_read(MSR_TURBO_RATIO_LIMIT);
345 perf_ctl.lo = (msr.lo & 0xff) << 8;
346 } else if (cpu_config_tdp_levels()) {
347 /* Set to nominal TDP ratio */
348 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
349 perf_ctl.lo = (msr.lo & 0xff) << 8;
350 } else {
351 /* Platform Info bits 15:8 give max ratio */
352 msr = msr_read(MSR_PLATFORM_INFO);
353 perf_ctl.lo = msr.lo & 0xff00;
354 }
355 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
356
357 debug("cpu: frequency set to %d\n",
358 ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
359 }
360
broadwell_init(struct udevice * dev)361 int broadwell_init(struct udevice *dev)
362 {
363 struct cpu_broadwell_priv *priv = dev_get_priv(dev);
364 int num_threads;
365 int num_cores;
366 msr_t msr;
367 int ret;
368
369 msr = msr_read(CORE_THREAD_COUNT_MSR);
370 num_threads = (msr.lo >> 0) & 0xffff;
371 num_cores = (msr.lo >> 16) & 0xffff;
372 debug("CPU has %u cores, %u threads enabled\n", num_cores,
373 num_threads);
374
375 priv->ht_disabled = num_threads == num_cores;
376
377 ret = bsp_init_before_ap_bringup(dev);
378 if (ret)
379 return ret;
380
381 set_max_ratio();
382
383 return ret;
384 }
385
configure_mca(void)386 static void configure_mca(void)
387 {
388 msr_t msr;
389 const unsigned int mcg_cap_msr = 0x179;
390 int i;
391 int num_banks;
392
393 msr = msr_read(mcg_cap_msr);
394 num_banks = msr.lo & 0xff;
395 msr.lo = 0;
396 msr.hi = 0;
397 /*
398 * TODO(adurbin): This should only be done on a cold boot. Also, some
399 * of these banks are core vs package scope. For now every CPU clears
400 * every bank
401 */
402 for (i = 0; i < num_banks; i++)
403 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
404 }
405
enable_lapic_tpr(void)406 static void enable_lapic_tpr(void)
407 {
408 msr_t msr;
409
410 msr = msr_read(MSR_PIC_MSG_CONTROL);
411 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
412 msr_write(MSR_PIC_MSG_CONTROL, msr);
413 }
414
configure_c_states(void)415 static void configure_c_states(void)
416 {
417 msr_t msr;
418
419 msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
420 msr.lo |= (1 << 31); /* Timed MWAIT Enable */
421 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
422 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
423 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
424 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
425 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
426 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
427 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
428 /* The deepest package c-state defaults to factory-configured value */
429 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
430
431 msr = msr_read(MSR_MISC_PWR_MGMT);
432 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
433 msr_write(MSR_MISC_PWR_MGMT, msr);
434
435 msr = msr_read(MSR_POWER_CTL);
436 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
437 msr.lo |= (1 << 1); /* C1E Enable */
438 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
439 msr_write(MSR_POWER_CTL, msr);
440
441 /* C-state Interrupt Response Latency Control 0 - package C3 latency */
442 msr.hi = 0;
443 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
444 msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
445
446 /* C-state Interrupt Response Latency Control 1 */
447 msr.hi = 0;
448 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
449 msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
450
451 /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
452 msr.hi = 0;
453 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
454 msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
455
456 /* C-state Interrupt Response Latency Control 3 - package C8 */
457 msr.hi = 0;
458 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
459 msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
460
461 /* C-state Interrupt Response Latency Control 4 - package C9 */
462 msr.hi = 0;
463 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
464 msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
465
466 /* C-state Interrupt Response Latency Control 5 - package C10 */
467 msr.hi = 0;
468 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
469 msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
470 }
471
configure_misc(void)472 static void configure_misc(void)
473 {
474 msr_t msr;
475
476 msr = msr_read(MSR_IA32_MISC_ENABLE);
477 msr.lo |= MISC_ENABLE_FAST_STRING;
478 msr.lo |= MISC_ENABLE_TM1;
479 msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
480 msr_write(MSR_IA32_MISC_ENABLE, msr);
481
482 /* Disable thermal interrupts */
483 msr.lo = 0;
484 msr.hi = 0;
485 msr_write(MSR_IA32_THERM_INTERRUPT, msr);
486
487 /* Enable package critical interrupt only */
488 msr.lo = 1 << 4;
489 msr.hi = 0;
490 msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
491 }
492
configure_dca_cap(void)493 static void configure_dca_cap(void)
494 {
495 struct cpuid_result cpuid_regs;
496 msr_t msr;
497
498 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
499 cpuid_regs = cpuid(1);
500 if (cpuid_regs.ecx & (1 << 18)) {
501 msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
502 msr.lo |= 1;
503 msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
504 }
505 }
506
set_energy_perf_bias(u8 policy)507 static void set_energy_perf_bias(u8 policy)
508 {
509 msr_t msr;
510 int ecx;
511
512 /* Determine if energy efficient policy is supported */
513 ecx = cpuid_ecx(0x6);
514 if (!(ecx & (1 << 3)))
515 return;
516
517 /* Energy Policy is bits 3:0 */
518 msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
519 msr.lo &= ~0xf;
520 msr.lo |= policy & 0xf;
521 msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
522
523 debug("cpu: energy policy set to %u\n", policy);
524 }
525
526 /* All CPUs including BSP will run the following function */
cpu_core_init(struct udevice * dev)527 static void cpu_core_init(struct udevice *dev)
528 {
529 /* Clear out pending MCEs */
530 configure_mca();
531
532 /* Enable the local cpu apics */
533 enable_lapic_tpr();
534
535 /* Configure C States */
536 configure_c_states();
537
538 /* Configure Enhanced SpeedStep and Thermal Sensors */
539 configure_misc();
540
541 /* Thermal throttle activation offset */
542 cpu_configure_thermal_target(dev);
543
544 /* Enable Direct Cache Access */
545 configure_dca_cap();
546
547 /* Set energy policy */
548 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
549
550 /* Enable Turbo */
551 turbo_enable();
552 }
553
554 /*
555 * Configure processor power limits if possible
556 * This must be done AFTER set of BIOS_RESET_CPL
557 */
cpu_set_power_limits(int power_limit_1_time)558 void cpu_set_power_limits(int power_limit_1_time)
559 {
560 msr_t msr;
561 msr_t limit;
562 uint power_unit;
563 uint tdp, min_power, max_power, max_time;
564 u8 power_limit_1_val;
565
566 msr = msr_read(MSR_PLATFORM_INFO);
567 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
568 power_limit_1_time = 28;
569
570 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
571 return;
572
573 /* Get units */
574 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
575 power_unit = 2 << ((msr.lo & 0xf) - 1);
576
577 /* Get power defaults for this SKU */
578 msr = msr_read(MSR_PKG_POWER_SKU);
579 tdp = msr.lo & 0x7fff;
580 min_power = (msr.lo >> 16) & 0x7fff;
581 max_power = msr.hi & 0x7fff;
582 max_time = (msr.hi >> 16) & 0x7f;
583
584 debug("CPU TDP: %u Watts\n", tdp / power_unit);
585
586 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
587 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
588
589 if (min_power > 0 && tdp < min_power)
590 tdp = min_power;
591
592 if (max_power > 0 && tdp > max_power)
593 tdp = max_power;
594
595 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
596
597 /* Set long term power limit to TDP */
598 limit.lo = 0;
599 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
600 limit.lo |= PKG_POWER_LIMIT_EN;
601 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
602 PKG_POWER_LIMIT_TIME_SHIFT;
603
604 /* Set short term power limit to 1.25 * TDP */
605 limit.hi = 0;
606 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
607 limit.hi |= PKG_POWER_LIMIT_EN;
608 /* Power limit 2 time is only programmable on server SKU */
609
610 msr_write(MSR_PKG_POWER_LIMIT, limit);
611
612 /* Set power limit values in MCHBAR as well */
613 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
614 writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
615
616 /* Set DDR RAPL power limit by copying from MMIO to MSR */
617 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
618 msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
619 msr_write(MSR_DDR_RAPL_LIMIT, msr);
620
621 /* Use nominal TDP values for CPUs with configurable TDP */
622 if (cpu_config_tdp_levels()) {
623 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
624 limit.hi = 0;
625 limit.lo = msr.lo & 0xff;
626 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
627 }
628 }
629
broadwell_get_info(const struct udevice * dev,struct cpu_info * info)630 static int broadwell_get_info(const struct udevice *dev, struct cpu_info *info)
631 {
632 return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
633 }
634
broadwell_get_count(const struct udevice * dev)635 static int broadwell_get_count(const struct udevice *dev)
636 {
637 return 4;
638 }
639
cpu_x86_broadwell_probe(struct udevice * dev)640 static int cpu_x86_broadwell_probe(struct udevice *dev)
641 {
642 if (dev_seq(dev) == 0) {
643 cpu_core_init(dev);
644 return broadwell_init(dev);
645 }
646
647 return 0;
648 }
649
650 static const struct cpu_ops cpu_x86_broadwell_ops = {
651 .get_desc = cpu_x86_get_desc,
652 .get_info = broadwell_get_info,
653 .get_count = broadwell_get_count,
654 .get_vendor = cpu_x86_get_vendor,
655 };
656
657 static const struct udevice_id cpu_x86_broadwell_ids[] = {
658 { .compatible = "intel,core-i3-gen5" },
659 { }
660 };
661
662 U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
663 .name = "cpu_x86_broadwell",
664 .id = UCLASS_CPU,
665 .of_match = cpu_x86_broadwell_ids,
666 .bind = cpu_x86_bind,
667 .probe = cpu_x86_broadwell_probe,
668 .ops = &cpu_x86_broadwell_ops,
669 .priv_auto = sizeof(struct cpu_broadwell_priv),
670 .flags = DM_FLAG_PRE_RELOC,
671 };
672