1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 Google, Inc
4 *
5 * From coreboot src/soc/intel/broadwell/romstage/raminit.c
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <init.h>
11 #include <log.h>
12 #include <pci.h>
13 #include <syscon.h>
14 #include <asm/cpu.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/lpc_common.h>
18 #include <asm/mrccache.h>
19 #include <asm/mrc_common.h>
20 #include <asm/mtrr.h>
21 #include <asm/pci.h>
22 #include <asm/arch/iomap.h>
23 #include <asm/arch/me.h>
24 #include <asm/arch/pch.h>
25 #include <asm/arch/pei_data.h>
26 #include <asm/arch/pm.h>
27
board_get_usable_ram_top(ulong total_size)28 ulong board_get_usable_ram_top(ulong total_size)
29 {
30 return mrc_common_board_get_usable_ram_top(total_size);
31 }
32
dram_init_banksize(void)33 int dram_init_banksize(void)
34 {
35 mrc_common_dram_init_banksize();
36
37 return 0;
38 }
39
get_top_of_ram(struct udevice * dev)40 static unsigned long get_top_of_ram(struct udevice *dev)
41 {
42 /*
43 * Base of DPR is top of usable DRAM below 4GiB. The register has
44 * 1 MiB alignment and reports the TOP of the range, the base
45 * must be calculated from the size in MiB in bits 11:4.
46 */
47 u32 dpr, tom;
48
49 dm_pci_read_config32(dev, DPR, &dpr);
50 tom = dpr & ~((1 << 20) - 1);
51
52 debug("dpt %08x tom %08x\n", dpr, tom);
53 /* Subtract DMA Protected Range size if enabled */
54 if (dpr & DPR_EPM)
55 tom -= (dpr & DPR_SIZE_MASK) << 16;
56
57 return (unsigned long)tom;
58 }
59
60 /**
61 * sdram_find() - Find available memory
62 *
63 * This is a bit complicated since on x86 there are system memory holes all
64 * over the place. We create a list of available memory blocks
65 *
66 * @dev: Northbridge device
67 */
sdram_find(struct udevice * dev)68 static int sdram_find(struct udevice *dev)
69 {
70 struct memory_info *info = &gd->arch.meminfo;
71 ulong top_of_ram;
72
73 top_of_ram = get_top_of_ram(dev);
74 mrc_add_memory_area(info, 0, top_of_ram);
75
76 /* Add MTRRs for memory */
77 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
78
79 return 0;
80 }
81
prepare_mrc_cache(struct pei_data * pei_data)82 static int prepare_mrc_cache(struct pei_data *pei_data)
83 {
84 struct mrc_data_container *mrc_cache;
85 struct mrc_region entry;
86 int ret;
87
88 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
89 if (ret)
90 return ret;
91 mrc_cache = mrccache_find_current(&entry);
92 if (!mrc_cache)
93 return -ENOENT;
94
95 pei_data->saved_data = mrc_cache->data;
96 pei_data->saved_data_size = mrc_cache->data_size;
97 debug("%s: at %p, size %x checksum %04x\n", __func__,
98 pei_data->saved_data, pei_data->saved_data_size,
99 mrc_cache->checksum);
100
101 return 0;
102 }
103
dram_init(void)104 int dram_init(void)
105 {
106 struct pei_data _pei_data __aligned(8);
107 struct pei_data *pei_data = &_pei_data;
108 struct udevice *dev, *me_dev, *pch_dev;
109 struct chipset_power_state ps;
110 const void *spd_data;
111 int ret, size;
112
113 memset(pei_data, '\0', sizeof(struct pei_data));
114
115 /* Print ME state before MRC */
116 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
117 if (ret) {
118 debug("Cannot get ME (err=%d)\n", ret);
119 return ret;
120 }
121 intel_me_status(me_dev);
122
123 /* Save ME HSIO version */
124 ret = uclass_first_device_err(UCLASS_PCH, &pch_dev);
125 if (ret) {
126 debug("Cannot get PCH (err=%d)\n", ret);
127 return ret;
128 }
129 power_state_get(pch_dev, &ps);
130
131 intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
132
133 broadwell_fill_pei_data(pei_data);
134 mainboard_fill_pei_data(pei_data);
135
136 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
137 if (ret) {
138 debug("Cannot get Northbridge (err=%d)\n", ret);
139 return ret;
140 }
141 size = 256;
142 ret = mrc_locate_spd(dev, size, &spd_data);
143 if (ret) {
144 debug("Cannot locate SPD (err=%d)\n", ret);
145 return ret;
146 }
147 memcpy(pei_data->spd_data[0][0], spd_data, size);
148 memcpy(pei_data->spd_data[1][0], spd_data, size);
149
150 ret = prepare_mrc_cache(pei_data);
151 if (ret)
152 debug("prepare_mrc_cache failed: %d\n", ret);
153
154 debug("PEI version %#x\n", pei_data->pei_version);
155 ret = mrc_common_init(dev, pei_data, true);
156 if (ret) {
157 debug("mrc_common_init() failed(err=%d)\n", ret);
158 return ret;
159 }
160 debug("Memory init done\n");
161
162 ret = sdram_find(dev);
163 if (ret) {
164 debug("sdram_find() failed (err=%d)\n", ret);
165 return ret;
166 }
167 gd->ram_size = gd->arch.meminfo.total_32bit_memory;
168 debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
169
170 debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
171 pei_data->data_to_save);
172 /* S3 resume: don't save scrambler seed or MRC data */
173 if (pei_data->boot_mode != SLEEP_STATE_S3) {
174 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
175
176 /*
177 * This will be copied to SDRAM in reserve_arch(), then written
178 * to SPI flash in mrccache_save()
179 */
180 mrc->buf = (char *)pei_data->data_to_save;
181 mrc->len = pei_data->data_to_save_size;
182 }
183 gd->arch.pei_meminfo = pei_data->meminfo;
184
185 return 0;
186 }
187
188 /* Use this hook to save our SDRAM parameters */
misc_init_r(void)189 int misc_init_r(void)
190 {
191 int ret;
192
193 ret = mrccache_save();
194 if (ret)
195 printf("Unable to save MRC data: %d\n", ret);
196 else
197 debug("Saved MRC cache data\n");
198
199 return 0;
200 }
201
202 static const struct udevice_id broadwell_syscon_ids[] = {
203 { .compatible = "intel,me", .data = X86_SYSCON_ME },
204 { }
205 };
206
207 U_BOOT_DRIVER(syscon_intel_me) = {
208 .name = "intel_me_syscon",
209 .id = UCLASS_SYSCON,
210 .of_match = broadwell_syscon_ids,
211 };
212