1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2017 Intel Corp.
4 * Copyright 2019 Google LLC
5 * Taken from coreboot file exit_car.S
6 */
7
8#include <config.h>
9#include <asm/msr-index.h>
10#include <asm/mtrr.h>
11
12.text
13.global car_uninit
14car_uninit:
15
16	/*
17	 * Retrieve return address from stack as it will get trashed below if
18	 * execution is utilizing the cache-as-ram stack.
19	 */
20	pop	%ebx
21
22	/* Disable MTRRs */
23	mov	$(MTRR_DEF_TYPE_MSR), %ecx
24	rdmsr
25	and	$(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
26	wrmsr
27
28#ifdef CONFIG_INTEL_CAR_NEM
29.global car_nem_teardown
30car_nem_teardown:
31
32	/* invalidate cache contents */
33	invd
34
35	/* Knock down bit 1 then bit 0 of NEM control not combining steps */
36	mov	$(MSR_EVICT_CTL), %ecx
37	rdmsr
38	and	$(~(1 << 1)), %eax
39	wrmsr
40	and	$(~(1 << 0)), %eax
41	wrmsr
42
43#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
44.global car_cqos_teardown
45car_cqos_teardown:
46
47	/* Go back to all-evicting mode, set both masks to all-1s */
48	mov	$MSR_L2_QOS_MASK(0), %ecx
49	rdmsr
50	mov	$~0, %al
51	wrmsr
52
53	mov	$MSR_L2_QOS_MASK(1), %ecx
54	rdmsr
55	mov	$~0, %al
56	wrmsr
57
58	/* Reset CLOS selector to 0 */
59	mov	$MSR_IA32_PQR_ASSOC, %ecx
60	rdmsr
61	and	$~MSR_IA32_PQR_ASSOC_MASK, %edx
62	wrmsr
63
64#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
65.global car_nem_enhanced_teardown
66car_nem_enhanced_teardown:
67
68	/* invalidate cache contents */
69	invd
70
71	/* Knock down bit 1 then bit 0 of NEM control not combining steps */
72	mov	$(MSR_EVICT_CTL), %ecx
73	rdmsr
74	and	$(~(1 << 1)), %eax
75	wrmsr
76	and	$(~(1 << 0)), %eax
77	wrmsr
78
79	/* Reset CLOS selector to 0 */
80	mov	$IA32_PQR_ASSOC, %ecx
81	rdmsr
82	and	$~IA32_PQR_ASSOC_MASK, %edx
83	wrmsr
84#endif
85
86	/* Return to caller */
87	jmp	*%ebx
88