1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * From Coreboot src/northbridge/intel/sandybridge/report_platform.c
4  *
5  * Copyright (C) 2012 Google Inc.
6  */
7 
8 #include <common.h>
9 #include <log.h>
10 #include <asm/cpu.h>
11 #include <asm/pci.h>
12 #include <asm/report_platform.h>
13 #include <asm/arch/pch.h>
14 
report_cpu_info(void)15 static void report_cpu_info(void)
16 {
17 	char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
18 	const char *mode[] = {"NOT ", ""};
19 	struct cpuid_result cpuidr;
20 	int vt, txt, aes;
21 	u32 index;
22 
23 	index = 0x80000000;
24 	cpuidr = cpuid(index);
25 	if (cpuidr.eax < 0x80000004) {
26 		strcpy(cpu_string, "Platform info not available");
27 		cpu_name = cpu_string;
28 	} else {
29 		cpu_name = cpu_get_name(cpu_string);
30 	}
31 
32 	cpuidr = cpuid(1);
33 	debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
34 	aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
35 	txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
36 	vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
37 	debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
38 	      mode[aes], mode[txt], mode[vt]);
39 }
40 
41 /* The PCI id name match comes from Intel document 472178 */
42 static struct {
43 	u16 dev_id;
44 	const char *dev_name;
45 } pch_table[] = {
46 	{0x1E41, "Desktop Sample"},
47 	{0x1E42, "Mobile Sample"},
48 	{0x1E43, "SFF Sample"},
49 	{0x1E44, "Z77"},
50 	{0x1E45, "H71"},
51 	{0x1E46, "Z75"},
52 	{0x1E47, "Q77"},
53 	{0x1E48, "Q75"},
54 	{0x1E49, "B75"},
55 	{0x1E4A, "H77"},
56 	{0x1E53, "C216"},
57 	{0x1E55, "QM77"},
58 	{0x1E56, "QS77"},
59 	{0x1E58, "UM77"},
60 	{0x1E57, "HM77"},
61 	{0x1E59, "HM76"},
62 	{0x1E5D, "HM75"},
63 	{0x1E5E, "HM70"},
64 	{0x1E5F, "NM70"},
65 };
66 
report_pch_info(struct udevice * dev)67 static void report_pch_info(struct udevice *dev)
68 {
69 	const char *pch_type = "Unknown";
70 	int i;
71 	u16 dev_id;
72 	uint8_t rev_id;
73 
74 	dm_pci_read_config16(dev, 2, &dev_id);
75 	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
76 		if (pch_table[i].dev_id == dev_id) {
77 			pch_type = pch_table[i].dev_name;
78 			break;
79 		}
80 	}
81 	dm_pci_read_config8(dev, 8, &rev_id);
82 	debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
83 	      rev_id);
84 }
85 
report_platform_info(struct udevice * dev)86 void report_platform_info(struct udevice *dev)
87 {
88 	report_cpu_info();
89 	report_pch_info(dev);
90 }
91