1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <init.h>
9 #include <pci.h>
10 #include <qfw.h>
11 #include <asm/irq.h>
12 #include <asm/post.h>
13 #include <asm/processor.h>
14 #include <asm/arch/device.h>
15 #include <asm/arch/qemu.h>
16
17 static bool i440fx;
18
19 #ifdef CONFIG_QFW
20
21 /* on x86, the qfw registers are all IO ports */
22 #define FW_CONTROL_PORT 0x510
23 #define FW_DATA_PORT 0x511
24 #define FW_DMA_PORT_LOW 0x514
25 #define FW_DMA_PORT_HIGH 0x518
26
qemu_x86_fwcfg_read_entry_pio(uint16_t entry,uint32_t size,void * address)27 static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
28 uint32_t size, void *address)
29 {
30 uint32_t i = 0;
31 uint8_t *data = address;
32
33 /*
34 * writting FW_CFG_INVALID will cause read operation to resume at
35 * last offset, otherwise read will start at offset 0
36 *
37 * Note: on platform where the control register is IO port, the
38 * endianness is little endian.
39 */
40 if (entry != FW_CFG_INVALID)
41 outw(cpu_to_le16(entry), FW_CONTROL_PORT);
42
43 /* the endianness of data register is string-preserving */
44 while (size--)
45 data[i++] = inb(FW_DATA_PORT);
46 }
47
qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access * dma)48 static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
49 {
50 /* the DMA address register is big endian */
51 outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
52
53 while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
54 __asm__ __volatile__ ("pause");
55 }
56
57 static struct fw_cfg_arch_ops fwcfg_x86_ops = {
58 .arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
59 .arch_read_dma = qemu_x86_fwcfg_read_entry_dma
60 };
61 #endif
62
enable_pm_piix(void)63 static void enable_pm_piix(void)
64 {
65 u8 en;
66 u16 cmd;
67
68 /* Set the PM I/O base */
69 pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
70
71 /* Enable access to the PM I/O space */
72 pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
73 cmd |= PCI_COMMAND_IO;
74 pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
75
76 /* PM I/O Space Enable (PMIOSE) */
77 pci_read_config8(PIIX_PM, PMREGMISC, &en);
78 en |= PMIOSE;
79 pci_write_config8(PIIX_PM, PMREGMISC, en);
80 }
81
enable_pm_ich9(void)82 static void enable_pm_ich9(void)
83 {
84 /* Set the PM I/O base */
85 pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
86 }
87
qemu_chipset_init(void)88 static void qemu_chipset_init(void)
89 {
90 u16 device, xbcs;
91 int pam, i;
92
93 /*
94 * i440FX and Q35 chipset have different PAM register offset, but with
95 * the same bitfield layout. Here we determine the offset based on its
96 * PCI device ID.
97 */
98 pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
99 i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
100 pam = i440fx ? I440FX_PAM : Q35_PAM;
101
102 /*
103 * Initialize Programmable Attribute Map (PAM) Registers
104 *
105 * Configure legacy segments C/D/E/F to system RAM
106 */
107 for (i = 0; i < PAM_NUM; i++)
108 pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
109
110 if (i440fx) {
111 /*
112 * Enable legacy IDE I/O ports decode
113 *
114 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
115 * However Linux ata_piix driver does sanity check on these two
116 * registers to see whether legacy ports decode is turned on.
117 * This is to make Linux ata_piix driver happy.
118 */
119 pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
120 pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
121
122 /* Enable I/O APIC */
123 pci_read_config16(PIIX_ISA, XBCS, &xbcs);
124 xbcs |= APIC_EN;
125 pci_write_config16(PIIX_ISA, XBCS, xbcs);
126
127 enable_pm_piix();
128 } else {
129 /* Configure PCIe ECAM base address */
130 pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
131 CONFIG_PCIE_ECAM_BASE | BAR_EN);
132
133 enable_pm_ich9();
134 }
135
136 #ifdef CONFIG_QFW
137 qemu_fwcfg_init(&fwcfg_x86_ops);
138 #endif
139 }
140
141 #if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
arch_cpu_init(void)142 int arch_cpu_init(void)
143 {
144 post_code(POST_CPU_INIT);
145
146 return x86_cpu_init_f();
147 }
148
checkcpu(void)149 int checkcpu(void)
150 {
151 return 0;
152 }
153
print_cpuinfo(void)154 int print_cpuinfo(void)
155 {
156 post_code(POST_CPU_INFO);
157 return default_print_cpuinfo();
158 }
159 #endif
160
arch_early_init_r(void)161 int arch_early_init_r(void)
162 {
163 qemu_chipset_init();
164
165 return 0;
166 }
167
168 #ifdef CONFIG_GENERATE_MP_TABLE
mp_determine_pci_dstirq(int bus,int dev,int func,int pirq)169 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
170 {
171 u8 irq;
172
173 if (i440fx) {
174 /*
175 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
176 * connected to I/O APIC INTPIN#16-19. Instead they are routed
177 * to an irq number controled by the PIRQ routing register.
178 */
179 pci_read_config8(PCI_BDF(bus, dev, func),
180 PCI_INTERRUPT_LINE, &irq);
181 } else {
182 /*
183 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
184 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
185 */
186 irq = pirq < 8 ? pirq + 16 : pirq + 12;
187 }
188
189 return irq;
190 }
191 #endif
192