1 // SPDX-License-Identifier: Intel
2 /*
3  * Copyright (C) 2013, Intel Corporation
4  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
5  *
6  * Ported from Intel released Quark UEFI BIOS
7  * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
8  */
9 
10 /*
11  * This is the main Quark Memory Reference Code (MRC)
12  *
13  * These functions are generic and should work for any Quark-based board.
14  *
15  * MRC requires two data structures to be passed in which are initialized by
16  * mrc_adjust_params().
17  *
18  * The basic flow is as follows:
19  * 01) Check for supported DDR speed configuration
20  * 02) Set up Memory Manager buffer as pass-through (POR)
21  * 03) Set Channel Interleaving Mode and Channel Stride to the most aggressive
22  *     setting possible
23  * 04) Set up the Memory Controller logic
24  * 05) Set up the DDR_PHY logic
25  * 06) Initialise the DRAMs (JEDEC)
26  * 07) Perform the Receive Enable Calibration algorithm
27  * 08) Perform the Write Leveling algorithm
28  * 09) Perform the Read Training algorithm (includes internal Vref)
29  * 10) Perform the Write Training algorithm
30  * 11) Set Channel Interleaving Mode and Channel Stride to the desired settings
31  *
32  * DRAM unit configuration based on Valleyview MRC.
33  */
34 
35 #include <common.h>
36 #include <version.h>
37 #include <asm/arch/mrc.h>
38 #include <asm/arch/msg_port.h>
39 #include "mrc_util.h"
40 #include "smc.h"
41 
42 static const struct mem_init init[] = {
43 	{ 0x0101, BM_COLD | BM_FAST | BM_WARM | BM_S3, clear_self_refresh       },
44 	{ 0x0200, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_timing_control  },
45 	{ 0x0103, BM_COLD | BM_FAST                  , prog_decode_before_jedec },
46 	{ 0x0104, BM_COLD | BM_FAST                  , perform_ddr_reset        },
47 	{ 0x0300, BM_COLD | BM_FAST           | BM_S3, ddrphy_init              },
48 	{ 0x0400, BM_COLD | BM_FAST                  , perform_jedec_init       },
49 	{ 0x0105, BM_COLD | BM_FAST                  , set_ddr_init_complete    },
50 	{ 0x0106,           BM_FAST | BM_WARM | BM_S3, restore_timings          },
51 	{ 0x0106, BM_COLD                            , default_timings          },
52 	{ 0x0500, BM_COLD                            , rcvn_cal                 },
53 	{ 0x0600, BM_COLD                            , wr_level                 },
54 	{ 0x0120, BM_COLD                            , prog_page_ctrl           },
55 	{ 0x0700, BM_COLD                            , rd_train                 },
56 	{ 0x0800, BM_COLD                            , wr_train                 },
57 	{ 0x010b, BM_COLD                            , store_timings            },
58 	{ 0x010c, BM_COLD | BM_FAST | BM_WARM | BM_S3, enable_scrambling        },
59 	{ 0x010d, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_control         },
60 	{ 0x010e, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_dra_drb             },
61 	{ 0x010f,                     BM_WARM | BM_S3, perform_wake             },
62 	{ 0x0110, BM_COLD | BM_FAST | BM_WARM | BM_S3, change_refresh_period    },
63 	{ 0x0111, BM_COLD | BM_FAST | BM_WARM | BM_S3, set_auto_refresh         },
64 	{ 0x0112, BM_COLD | BM_FAST | BM_WARM | BM_S3, ecc_enable               },
65 	{ 0x0113, BM_COLD | BM_FAST                  , memory_test              },
66 	{ 0x0114, BM_COLD | BM_FAST | BM_WARM | BM_S3, lock_registers           }
67 };
68 
69 /* Adjust configuration parameters before initialization sequence */
mrc_adjust_params(struct mrc_params * mrc_params)70 static void mrc_adjust_params(struct mrc_params *mrc_params)
71 {
72 	const struct dram_params *dram_params;
73 	uint8_t dram_width;
74 	uint32_t rank_enables;
75 	uint32_t channel_width;
76 
77 	ENTERFN();
78 
79 	/* initially expect success */
80 	mrc_params->status = MRC_SUCCESS;
81 
82 	dram_width = mrc_params->dram_width;
83 	rank_enables = mrc_params->rank_enables;
84 	channel_width = mrc_params->channel_width;
85 
86 	/*
87 	 * Setup board layout (must be reviewed as is selecting static timings)
88 	 * 0 == R0 (DDR3 x16), 1 == R1 (DDR3 x16),
89 	 * 2 == DV (DDR3 x8), 3 == SV (DDR3 x8).
90 	 */
91 	if (dram_width == X8)
92 		mrc_params->board_id = 2;	/* select x8 layout */
93 	else
94 		mrc_params->board_id = 0;	/* select x16 layout */
95 
96 	/* initially no memory */
97 	mrc_params->mem_size = 0;
98 
99 	/* begin of channel settings */
100 	dram_params = &mrc_params->params;
101 
102 	/*
103 	 * Determine column bits:
104 	 *
105 	 * Column: 11 for 8Gbx8, else 10
106 	 */
107 	mrc_params->column_bits[0] =
108 		(dram_params[0].density == 4) &&
109 		(dram_width == X8) ? 11 : 10;
110 
111 	/*
112 	 * Determine row bits:
113 	 *
114 	 * 512Mbx16=12 512Mbx8=13
115 	 * 1Gbx16=13   1Gbx8=14
116 	 * 2Gbx16=14   2Gbx8=15
117 	 * 4Gbx16=15   4Gbx8=16
118 	 * 8Gbx16=16   8Gbx8=16
119 	 */
120 	mrc_params->row_bits[0] = 12 + dram_params[0].density +
121 		(dram_params[0].density < 4) &&
122 		(dram_width == X8) ? 1 : 0;
123 
124 	/*
125 	 * Determine per-channel memory size:
126 	 *
127 	 * (For 2 RANKs, multiply by 2)
128 	 * (For 16 bit data bus, divide by 2)
129 	 *
130 	 * DENSITY WIDTH MEM_AVAILABLE
131 	 * 512Mb   x16   0x008000000 ( 128MB)
132 	 * 512Mb   x8    0x010000000 ( 256MB)
133 	 * 1Gb     x16   0x010000000 ( 256MB)
134 	 * 1Gb     x8    0x020000000 ( 512MB)
135 	 * 2Gb     x16   0x020000000 ( 512MB)
136 	 * 2Gb     x8    0x040000000 (1024MB)
137 	 * 4Gb     x16   0x040000000 (1024MB)
138 	 * 4Gb     x8    0x080000000 (2048MB)
139 	 */
140 	mrc_params->channel_size[0] = 1 << dram_params[0].density;
141 	mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1;
142 	mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1;
143 	mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2;
144 
145 	/* Determine memory size (convert number of 64MB/512Mb units) */
146 	mrc_params->mem_size += mrc_params->channel_size[0] << 26;
147 
148 	LEAVEFN();
149 }
150 
mrc_mem_init(struct mrc_params * mrc_params)151 static void mrc_mem_init(struct mrc_params *mrc_params)
152 {
153 	int i;
154 
155 	ENTERFN();
156 
157 	/* MRC started */
158 	mrc_post_code(0x01, 0x00);
159 
160 	if (mrc_params->boot_mode != BM_COLD) {
161 		if (mrc_params->ddr_speed != mrc_params->timings.ddr_speed) {
162 			/* full training required as frequency changed */
163 			mrc_params->boot_mode = BM_COLD;
164 		}
165 	}
166 
167 	for (i = 0; i < ARRAY_SIZE(init); i++) {
168 		uint64_t my_tsc;
169 
170 		if (mrc_params->boot_mode & init[i].boot_path) {
171 			uint8_t major = init[i].post_code >> 8 & 0xff;
172 			uint8_t minor = init[i].post_code >> 0 & 0xff;
173 			mrc_post_code(major, minor);
174 
175 			my_tsc = rdtsc();
176 			init[i].init_fn(mrc_params);
177 			DPF(D_TIME, "Execution time %llx", rdtsc() - my_tsc);
178 		}
179 	}
180 
181 	/* display the timings */
182 	print_timings(mrc_params);
183 
184 	/* MRC complete */
185 	mrc_post_code(0x01, 0xff);
186 
187 	LEAVEFN();
188 }
189 
mrc_init(struct mrc_params * mrc_params)190 void mrc_init(struct mrc_params *mrc_params)
191 {
192 	ENTERFN();
193 
194 	DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION,
195 	    U_BOOT_DATE, U_BOOT_TIME);
196 
197 	/* Set up the data structures used by mrc_mem_init() */
198 	mrc_adjust_params(mrc_params);
199 
200 	/* Initialize system memory */
201 	mrc_mem_init(mrc_params);
202 
203 	LEAVEFN();
204 }
205