1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
5 */
6
7/dts-v1/;
8
9#include <asm/arch-baytrail/fsp/fsp_configs.h>
10#include <dt-bindings/gpio/x86-gpio.h>
11#include <dt-bindings/interrupt-router/intel-irq.h>
12
13/include/ "skeleton.dtsi"
14/include/ "serial.dtsi"
15/include/ "reset.dtsi"
16/include/ "rtc.dtsi"
17/include/ "tsc_timer.dtsi"
18
19#include "smbios.dtsi"
20
21/ {
22	model = "Advantech SOM-DB5800-SOM-6867";
23	compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
24
25	aliases {
26		serial0 = &serial;
27		spi0 = &spi;
28	};
29
30	config {
31		silent_console = <0>;
32	};
33
34	pch_pinctrl {
35		compatible = "intel,x86-pinctrl";
36		reg = <0 0>;
37
38		/* HDA_RSTB */
39		soc_gpio_s0_8@0 {
40			pad-offset = <0x220>;
41			mode-func = <2>;
42		};
43
44		/* HDA_SYNC */
45		soc_gpio_s0_9@0 {
46			pad-offset = <0x250>;
47			mode-func = <2>;
48			pull-assign = <1>;
49		};
50
51		/* HDA_CLK */
52		soc_gpio_s0_10@0 {
53			pad-offset = <0x240>;
54			mode-func = <2>;
55		};
56
57		/* HDA_SDO */
58		soc_gpio_s0_11@0 {
59			pad-offset = <0x260>;
60			mode-func = <2>;
61			pull-assign = <1>;
62		};
63
64		/* HDA_SDI0 */
65		soc_gpio_s0_12@0 {
66			pad-offset = <0x270>;
67			mode-func = <2>;
68		};
69
70		/* SERIRQ */
71		soc_gpio_s0_50@0 {
72			pad-offset = <0x560>;
73			mode-func = <1>;
74		};
75	};
76
77	chosen {
78		stdout-path = "/serial";
79	};
80
81	cpus {
82		#address-cells = <1>;
83		#size-cells = <0>;
84
85		cpu@0 {
86			device_type = "cpu";
87			compatible = "intel,baytrail-cpu";
88			reg = <0>;
89			intel,apic-id = <0>;
90		};
91
92		cpu@1 {
93			device_type = "cpu";
94			compatible = "intel,baytrail-cpu";
95			reg = <1>;
96			intel,apic-id = <2>;
97		};
98
99		cpu@2 {
100			device_type = "cpu";
101			compatible = "intel,baytrail-cpu";
102			reg = <2>;
103			intel,apic-id = <4>;
104		};
105
106		cpu@3 {
107			device_type = "cpu";
108			compatible = "intel,baytrail-cpu";
109			reg = <3>;
110			intel,apic-id = <6>;
111		};
112
113	};
114
115	pci {
116		compatible = "intel,pci-baytrail", "pci-x86";
117		#address-cells = <3>;
118		#size-cells = <2>;
119		u-boot,dm-pre-reloc;
120		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
121			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
122			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
123
124		pch@1f,0 {
125			reg = <0x0000f800 0 0 0 0>;
126			compatible = "pci8086,0f1c", "intel,pch9";
127			#address-cells = <1>;
128			#size-cells = <1>;
129
130			irq-router {
131				compatible = "intel,irq-router";
132				intel,pirq-config = "ibase";
133				intel,ibase-offset = <0x50>;
134				intel,actl-addr = <0>;
135				intel,pirq-link = <8 8>;
136				intel,pirq-mask = <0xdee0>;
137				intel,pirq-routing = <
138					/* BayTrail PCI devices */
139					PCI_BDF(0, 2, 0) INTA PIRQA
140					PCI_BDF(0, 3, 0) INTA PIRQA
141					PCI_BDF(0, 16, 0) INTA PIRQA
142					PCI_BDF(0, 17, 0) INTA PIRQA
143					PCI_BDF(0, 18, 0) INTA PIRQA
144					PCI_BDF(0, 19, 0) INTA PIRQA
145					PCI_BDF(0, 20, 0) INTA PIRQA
146					PCI_BDF(0, 21, 0) INTA PIRQA
147					PCI_BDF(0, 22, 0) INTA PIRQA
148					PCI_BDF(0, 23, 0) INTA PIRQA
149					PCI_BDF(0, 24, 0) INTA PIRQA
150					PCI_BDF(0, 24, 1) INTC PIRQC
151					PCI_BDF(0, 24, 2) INTD PIRQD
152					PCI_BDF(0, 24, 3) INTB PIRQB
153					PCI_BDF(0, 24, 4) INTA PIRQA
154					PCI_BDF(0, 24, 5) INTC PIRQC
155					PCI_BDF(0, 24, 6) INTD PIRQD
156					PCI_BDF(0, 24, 7) INTB PIRQB
157					PCI_BDF(0, 26, 0) INTA PIRQA
158					PCI_BDF(0, 27, 0) INTA PIRQA
159					PCI_BDF(0, 28, 0) INTA PIRQA
160					PCI_BDF(0, 28, 1) INTB PIRQB
161					PCI_BDF(0, 28, 2) INTC PIRQC
162					PCI_BDF(0, 28, 3) INTD PIRQD
163					PCI_BDF(0, 29, 0) INTA PIRQA
164					PCI_BDF(0, 30, 0) INTA PIRQA
165					PCI_BDF(0, 30, 1) INTD PIRQD
166					PCI_BDF(0, 30, 2) INTB PIRQB
167					PCI_BDF(0, 30, 3) INTC PIRQC
168					PCI_BDF(0, 30, 4) INTD PIRQD
169					PCI_BDF(0, 30, 5) INTB PIRQB
170					PCI_BDF(0, 31, 3) INTB PIRQB
171
172					/*
173					 * PCIe root ports downstream
174					 * interrupts
175					 */
176					PCI_BDF(1, 0, 0) INTA PIRQA
177					PCI_BDF(1, 0, 0) INTB PIRQB
178					PCI_BDF(1, 0, 0) INTC PIRQC
179					PCI_BDF(1, 0, 0) INTD PIRQD
180					PCI_BDF(2, 0, 0) INTA PIRQB
181					PCI_BDF(2, 0, 0) INTB PIRQC
182					PCI_BDF(2, 0, 0) INTC PIRQD
183					PCI_BDF(2, 0, 0) INTD PIRQA
184					PCI_BDF(3, 0, 0) INTA PIRQC
185					PCI_BDF(3, 0, 0) INTB PIRQD
186					PCI_BDF(3, 0, 0) INTC PIRQA
187					PCI_BDF(3, 0, 0) INTD PIRQB
188					PCI_BDF(4, 0, 0) INTA PIRQD
189					PCI_BDF(4, 0, 0) INTB PIRQA
190					PCI_BDF(4, 0, 0) INTC PIRQB
191					PCI_BDF(4, 0, 0) INTD PIRQC
192				>;
193			};
194
195			spi: spi {
196				#address-cells = <1>;
197				#size-cells = <0>;
198				compatible = "intel,ich9-spi";
199				spi-flash@0 {
200					#address-cells = <1>;
201					#size-cells = <1>;
202					reg = <0>;
203					compatible = "macronix,mx25l6405d",
204						"jedec,spi-nor";
205					memory-map = <0xff800000 0x00800000>;
206					rw-mrc-cache {
207						label = "rw-mrc-cache";
208						reg = <0x006f0000 0x00010000>;
209					};
210				};
211			};
212
213			gpioa {
214				compatible = "intel,ich6-gpio";
215				u-boot,dm-pre-reloc;
216				reg = <0 0x20>;
217				bank-name = "A";
218				use-lvl-write-cache;
219			};
220
221			gpiob {
222				compatible = "intel,ich6-gpio";
223				u-boot,dm-pre-reloc;
224				reg = <0x20 0x20>;
225				bank-name = "B";
226				use-lvl-write-cache;
227			};
228
229			gpioc {
230				compatible = "intel,ich6-gpio";
231				u-boot,dm-pre-reloc;
232				reg = <0x40 0x20>;
233				bank-name = "C";
234				use-lvl-write-cache;
235			};
236
237			gpiod {
238				compatible = "intel,ich6-gpio";
239				u-boot,dm-pre-reloc;
240				reg = <0x60 0x20>;
241				bank-name = "D";
242				use-lvl-write-cache;
243			};
244
245			gpioe {
246				compatible = "intel,ich6-gpio";
247				u-boot,dm-pre-reloc;
248				reg = <0x80 0x20>;
249				bank-name = "E";
250				use-lvl-write-cache;
251			};
252
253			gpiof {
254				compatible = "intel,ich6-gpio";
255				u-boot,dm-pre-reloc;
256				reg = <0xA0 0x20>;
257				bank-name = "F";
258				use-lvl-write-cache;
259			};
260		};
261	};
262
263	fsp {
264		compatible = "intel,baytrail-fsp";
265		fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
266		fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
267		fsp,mrc-init-spd-addr1 = <0xa0>;
268		fsp,mrc-init-spd-addr2 = <0xa2>;
269		fsp,enable-spi;
270		fsp,enable-sata;
271		fsp,sata-mode = <SATA_MODE_AHCI>;
272		fsp,enable-azalia;
273		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
274		fsp,enable-dma0;
275		fsp,enable-dma1;
276		fsp,enable-i2c0;
277		fsp,enable-i2c1;
278		fsp,enable-i2c2;
279		fsp,enable-i2c3;
280		fsp,enable-i2c4;
281		fsp,enable-i2c5;
282		fsp,enable-i2c6;
283		fsp,enable-pwm0;
284		fsp,enable-pwm1;
285		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
286		fsp,aperture-size = <APERTURE_SIZE_256MB>;
287		fsp,gtt-size = <GTT_SIZE_2MB>;
288		fsp,scc-mode = <SCC_MODE_PCI>;
289		fsp,os-selection = <OS_SELECTION_LINUX>;
290		fsp,enable-igd;
291	};
292
293	microcode {
294		update@0 {
295#include "microcode/m0130673325.dtsi"
296		};
297		update@1 {
298#include "microcode/m0130679907.dtsi"
299		};
300	};
301
302};
303