1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2014 Google Inc.
4 * Copyright (C) 2016 Intel Corporation.
5 */
6
7External (\_PR.CP00._PSS, PkgObj)
8External (\_PR.CP00._TSS, PkgObj)
9External (\_PR.CP00._TPC, MethodObj)
10External (\_PR.CP00._PTC, PkgObj)
11External (\_PR.CP00._TSD, PkgObj)
12External (\_SB.MPDL, IntObj)
13
14Device (DPTF_CPU_DEVICE)
15{
16	Name(_ADR, DPTF_CPU_ADDR)
17
18	Method (_STA)
19	{
20		If (LEqual (\DPTE, One)) {
21			Return (0xF)
22		} Else {
23			Return (0x0)
24		}
25	}
26
27	/*
28	 * Processor Throttling Controls
29	 */
30
31	Method (_TSS)
32	{
33		If (CondRefOf (\_PR.CP00._TSS)) {
34			Return (\_PR.CP00._TSS)
35		} Else {
36			Return (Package ()
37			{
38				Package () { 0, 0, 0, 0, 0 }
39			})
40		}
41	}
42
43	Method (_TPC)
44	{
45		If (CondRefOf (\_PR.CP00._TPC)) {
46			Return (\_PR.CP00._TPC)
47		} Else {
48			Return (0)
49		}
50	}
51
52	Method (_PTC)
53	{
54		If (CondRefOf (\_PR.CP00._PTC)) {
55			Return (\_PR.CP00._PTC)
56		} Else {
57			Return (Package ()
58			{
59				Buffer () { 0 },
60				Buffer () { 0 }
61			})
62		}
63	}
64
65	Method (_TSD)
66	{
67		If (CondRefOf (\_PR.CP00._TSD)) {
68			Return (\_PR.CP00._TSD)
69		} Else {
70			Return (Package ()
71			{
72				Package () { 5, 0, 0, 0, 0 }
73			})
74		}
75	}
76
77	Method (_TDL)
78	{
79		If (CondRefOf (\_PR.CP00._TSS)) {
80			Store (SizeOf (\_PR.CP00._TSS), Local0)
81			Decrement (Local0)
82			Return (Local0)
83		} Else {
84			Return (0)
85		}
86	}
87
88	/*
89	 * Processor Performance Control
90	 */
91
92	Method (_PPC)
93	{
94		Return (0)
95	}
96
97	Method (SPPC, 1)
98	{
99		Store (Arg0, \PPCM)
100
101		/* Notify OS to re-read _PPC limit on each CPU */
102		\PPCN ()
103	}
104
105	Method (_PSS)
106	{
107		If (CondRefOf (\_PR.CP00._PSS)) {
108			Return (\_PR.CP00._PSS)
109		} Else {
110			Return (Package ()
111			{
112				Package () { 0, 0, 0, 0, 0, 0 }
113			})
114		}
115	}
116
117
118	Method (_PDL)
119	{
120		/* Check for mainboard specific _PDL override */
121		If (CondRefOf (\_SB.MPDL)) {
122			Return (\_SB.MPDL)
123		} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
124			Store (SizeOf (\_PR.CP00._PSS), Local0)
125			Decrement (Local0)
126			Return (Local0)
127		} Else {
128			Return (0)
129		}
130	}
131
132	/* Return PPCC table defined by mainboard */
133	Method (PPCC)
134	{
135		Return (\_SB.MPPC)
136	}
137
138#ifdef DPTF_CPU_CRITICAL
139	Method (_CRT)
140	{
141		Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL))
142	}
143#endif
144
145#ifdef DPTF_CPU_PASSIVE
146	Method (_PSV)
147	{
148		Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE))
149	}
150#endif
151
152#ifdef DPTF_CPU_ACTIVE_AC0
153	Method (_AC0)
154	{
155		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0))
156	}
157#endif
158
159#ifdef DPTF_CPU_ACTIVE_AC1
160	Method (_AC1)
161	{
162		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1))
163	}
164#endif
165
166#ifdef DPTF_CPU_ACTIVE_AC2
167	Method (_AC2)
168	{
169		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2))
170	}
171#endif
172
173#ifdef DPTF_CPU_ACTIVE_AC3
174	Method (_AC3)
175	{
176		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3))
177	}
178#endif
179
180#ifdef DPTF_CPU_ACTIVE_AC4
181	Method (_AC4)
182	{
183		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4))
184	}
185#endif
186}
187