1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Intel Corp.
4 * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
5 */
6#include <asm/arch/gpio.h>
7#include <asm/intel_pinctrl_defs.h>
8// #include <intelblocks/pcr.h>
9// #include <soc/pcr_ids.h>
10#include <asm/arch/iomap.h>
11#include <p2sb.h>
12#include "gpiolib.asl"
13
14scope (\_SB) {
15
16	Device (GPO0)
17	{
18		Name (_HID, GPIO_COMM_NAME)
19		Name (_CID, GPIO_COMM_NAME)
20		Name (_DDN, GPIO_COMM_0_DESC)
21		Name (_UID, 1)
22
23		Name (RBUF, ResourceTemplate ()
24		{
25			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
26			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
27			{
28				GPIO_BANK_INT
29			}
30		})
31
32		Method (_CRS, 0x0, NotSerialized)
33		{
34			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
35			ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0)
36			Or (IOMAP_P2SB_BAR, Local0, RBAS)
37			Return (^RBUF)
38		}
39
40		Method (_STA, 0x0, NotSerialized)
41		{
42			Return(0xf)
43		}
44	}
45
46	Device (GPO1)
47	{
48		Name (_HID, GPIO_COMM_NAME)
49		Name (_CID, GPIO_COMM_NAME)
50		Name (_DDN, GPIO_COMM_1_DESC)
51		Name (_UID, 2)
52
53		Name (RBUF, ResourceTemplate ()
54		{
55			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
56			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
57			{
58				GPIO_BANK_INT
59			}
60		})
61
62		Method (_CRS, 0x0, NotSerialized)
63		{
64			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
65			ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0)
66			Or (IOMAP_P2SB_BAR, Local0, RBAS)
67			Return (^RBUF)
68		}
69
70		Method (_STA, 0x0, NotSerialized)
71		{
72			Return(0xf)
73		}
74	}
75
76	Device (GPO2)
77	{
78		Name (_HID, GPIO_COMM_NAME)
79		Name (_CID, GPIO_COMM_NAME)
80		Name (_DDN, GPIO_COMM_2_DESC)
81		Name (_UID, 3)
82
83		Name (RBUF, ResourceTemplate ()
84		{
85			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
86			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
87			{
88				GPIO_BANK_INT
89			}
90		})
91
92		Method (_CRS, 0x0, NotSerialized)
93		{
94			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
95			ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0)
96			Or (IOMAP_P2SB_BAR, Local0, RBAS)
97			Return (^RBUF)
98		}
99
100		Method (_STA, 0x0, NotSerialized)
101		{
102			Return(0xf)
103		}
104	}
105
106	Device (GPO3)
107	{
108		Name (_HID, GPIO_COMM_NAME)
109		Name (_CID, GPIO_COMM_NAME)
110		Name (_DDN, GPIO_COMM_3_DESC)
111		Name (_UID, 4)
112
113		Name (RBUF, ResourceTemplate ()
114		{
115			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
116			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
117			{
118				GPIO_BANK_INT
119			}
120		})
121
122		Method (_CRS, 0x0, NotSerialized)
123		{
124			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
125			ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0)
126			Or (IOMAP_P2SB_BAR, Local0, RBAS)
127			Return (^RBUF)
128		}
129
130		Method (_STA, 0x0, NotSerialized)
131		{
132			Return(0xf)
133		}
134	}
135
136	Scope(\_SB.PCI0) {
137		/* PERST Assertion
138		 * Note: PERST is Active High
139		 */
140		Method (PRAS, 0x1, Serialized)
141		{
142			/*
143			 * Assert PERST
144			 * local1 - to toggle Tx pin of Dw0
145			 * local2 - Address of PERST
146			 */
147			Store (Arg0, Local2)
148			Store (\_SB.GPC0 (Local2), Local1)
149			Or (Local1, PAD_CFG0_TX_STATE, Local1)
150			\_SB.SPC0 (Local2, Local1)
151		}
152
153		/* PERST DE-Assertion */
154		Method (PRDA, 0x1, Serialized)
155		{
156			/*
157			 * De-assert PERST
158			 * local1 - to toggle Tx pin of Dw0
159			 * local2 - Address of PERST
160			 */
161			Store (Arg0, Local2)
162			Store (\_SB.GPC0 (Local2), Local1)
163			And (Local1, Not (PAD_CFG0_TX_STATE), Local1)
164			\_SB.SPC0 (Local2, Local1)
165		}
166	}
167
168	/*
169	 * Sleep button device ASL code. We are using this device to
170	 * add the _PRW method for a dummy wake event to kernel so that
171	 * before going to sleep kernel does not clear bit 15 in ACPI
172	 * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit.
173	 */
174	Device (SLP)
175	{
176		Name (_HID, EisaId ("PNP0C0E"))
177
178		Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 })
179	}
180}
181
182Scope(\_GPE)
183{
184	/*
185	 * Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
186	 * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
187	 * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
188	 * GPE0a_EN at 0x430 is reserved.
189	 */
190	Method(_L0F, 0) {}
191}
192