1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2019 Google LLC 4 * Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com 5 */ 6 7 #ifndef __ASM_ARCH_FSP_BINDINGS_H 8 #define __ASM_ARCH_FSP_BINDINGS_H 9 10 #include <asm/arch/fsp/fsp_m_upd.h> 11 #include <asm/arch/fsp/fsp_s_upd.h> 12 13 #define ARRAY_SIZE_OF_MEMBER(s, m) (ARRAY_SIZE((((s *)0)->m))) 14 #define SIZE_OF_MEMBER(s, m) (sizeof((((s *)0)->m))) 15 16 enum conf_type { 17 FSP_UINT8, 18 FSP_UINT16, 19 FSP_UINT32, 20 FSP_UINT64, 21 FSP_STRING, 22 FSP_LPDDR4_SWIZZLE, 23 }; 24 25 /** 26 * struct fsp_binding - Binding describing devicetree/FSP relationships 27 * @offset: Offset within the FSP config structure 28 * @propname: Name of property to read 29 * @type: Type of the property to read 30 * @count: If the property is expected to be an array, this is the 31 * number of expected elements 32 * Set to 0 if the property is expected to be a scalar 33 * 34 * The struct fsp_binding is used to describe the relationship between 35 * values stored in devicetree and where they are placed in the FSP 36 * configuration structure. 37 */ 38 struct fsp_binding { 39 size_t offset; 40 char *propname; 41 enum conf_type type; 42 size_t count; 43 }; 44 45 /* 46 * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. 47 * There are four physical LPDDR4 channels, each 32-bits wide. There are two 48 * logical channels using two physical channels together to form a 64-bit 49 * interface to memory for each logical channel. 50 */ 51 52 enum { 53 LP4_PHYS_CH0A, 54 LP4_PHYS_CH0B, 55 LP4_PHYS_CH1A, 56 LP4_PHYS_CH1B, 57 58 LP4_NUM_PHYS_CHANNELS, 59 }; 60 61 /* 62 * The DQs within a physical channel can be bit-swizzled within each byte. 63 * Within a channel the bytes can be swapped, but the DQs need to be routed 64 * with the corresponding DQS (strobe). 65 */ 66 enum { 67 LP4_DQS0, 68 LP4_DQS1, 69 LP4_DQS2, 70 LP4_DQS3, 71 72 LP4_NUM_BYTE_LANES, 73 DQ_BITS_PER_DQS = 8, 74 }; 75 76 /* Provide bit swizzling per DQS and byte swapping within a channel */ 77 struct lpddr4_chan_swizzle_cfg { 78 u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS]; 79 }; 80 81 struct lpddr4_swizzle_cfg { 82 struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS]; 83 }; 84 85 /** 86 * fsp_m_update_config_from_dtb() - Read FSP-M config from devicetree node 87 * @node: Valid node reference to read property from 88 * @cfg: Pointer to FSP-M config structure 89 * @return 0 on success, -ve on error 90 * 91 * This function reads the configuration for FSP-M from the provided 92 * devicetree node and saves it in the FSP-M configuration structure. 93 * Configuration options that are not present in the devicetree are 94 * left at their current value. 95 */ 96 int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg); 97 98 /** 99 * fsp_s_update_config_from_dtb() - Read FSP-S config from devicetree node 100 * @node: Valid node reference to read property from 101 * @cfg: Pointer to FSP-S config structure 102 * @return 0 on success, -ve on error 103 * 104 * This function reads the configuration for FSP-S from the provided 105 * devicetree node and saves it in the FSP-S configuration structure. 106 * Configuration options that are not present in the devicetree are 107 * left at their current value. 108 */ 109 int fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config *cfg); 110 111 #endif 112