1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2016 Intel Corporation 4 * Copyright 2020 Google LLC 5 * 6 * Taken from coreboot apl gpe.h 7 */ 8 9 #ifndef _ASM_ARCH_GPE_H_ 10 #define _ASM_ARCH_GPE_H_ 11 12 /* bit position in GPE0a_STS register */ 13 #define GPE0A_PCIE_SCI_STS 0 14 #define GPE0A_SWGPE_STS 2 15 #define GPE0A_PCIE_WAKE0_STS 3 16 #define GPE0A_PUNIT_SCI_STS 4 17 #define GPE0A_PCIE_WAKE1_STS 6 18 #define GPE0A_PCIE_WAKE2_STS 7 19 #define GPE0A_PCIE_WAKE3_STS 8 20 #define GPE0A_PCIE_GPE_STS 9 21 #define GPE0A_BATLOW_STS 10 22 #define GPE0A_CSE_PME_STS 11 23 #define GPE0A_XDCI_PME_STS 12 24 #define GPE0A_XHCI_PME_STS 13 25 #define GPE0A_AVS_PME_STS 14 26 #define GPE0A_GPIO_TIER1_SCI_STS 15 27 #define GPE0A_SMB_WAK_STS 16 28 #define GPE0A_SATA_PME_STS 17 29 #define GPE0A_CNVI_PME_STS 18 30 31 /* Group DW0 is reserved in Apollolake */ 32 33 /* GPE_63_32 */ 34 #define GPE0_DW1_00 32 35 #define GPE0_DW1_01 33 36 #define GPE0_DW1_02 34 37 #define GPE0_DW1_03 36 38 #define GPE0_DW1_04 36 39 #define GPE0_DW1_05 37 40 #define GPE0_DW1_06 38 41 #define GPE0_DW1_07 39 42 #define GPE0_DW1_08 40 43 #define GPE0_DW1_09 41 44 #define GPE0_DW1_10 42 45 #define GPE0_DW1_11 43 46 #define GPE0_DW1_12 44 47 #define GPE0_DW1_13 45 48 #define GPE0_DW1_14 46 49 #define GPE0_DW1_15 47 50 #define GPE0_DW1_16 48 51 #define GPE0_DW1_17 49 52 #define GPE0_DW1_18 50 53 #define GPE0_DW1_19 51 54 #define GPE0_DW1_20 52 55 #define GPE0_DW1_21 53 56 #define GPE0_DW1_22 54 57 #define GPE0_DW1_23 55 58 #define GPE0_DW1_24 56 59 #define GPE0_DW1_25 57 60 #define GPE0_DW1_26 58 61 #define GPE0_DW1_27 59 62 #define GPE0_DW1_28 60 63 #define GPE0_DW1_29 61 64 #define GPE0_DW1_30 62 65 #define GPE0_DW1_31 63 66 /* GPE_95_64 */ 67 #define GPE0_DW2_00 64 68 #define GPE0_DW2_01 65 69 #define GPE0_DW2_02 66 70 #define GPE0_DW2_03 67 71 #define GPE0_DW2_04 68 72 #define GPE0_DW2_05 69 73 #define GPE0_DW2_06 70 74 #define GPE0_DW2_07 71 75 #define GPE0_DW2_08 72 76 #define GPE0_DW2_09 73 77 #define GPE0_DW2_10 74 78 #define GPE0_DW2_11 75 79 #define GPE0_DW2_12 76 80 #define GPE0_DW2_13 77 81 #define GPE0_DW2_14 78 82 #define GPE0_DW2_15 79 83 #define GPE0_DW2_16 80 84 #define GPE0_DW2_17 81 85 #define GPE0_DW2_18 82 86 #define GPE0_DW2_19 83 87 #define GPE0_DW2_20 84 88 #define GPE0_DW2_21 85 89 #define GPE0_DW2_22 86 90 #define GPE0_DW2_23 87 91 #define GPE0_DW2_24 88 92 #define GPE0_DW2_25 89 93 #define GPE0_DW2_26 90 94 #define GPE0_DW2_27 91 95 #define GPE0_DW2_28 92 96 #define GPE0_DW2_29 93 97 #define GPE0_DW2_30 94 98 #define GPE0_DW2_31 95 99 /* GPE_127_96 */ 100 #define GPE0_DW3_00 96 101 #define GPE0_DW3_01 97 102 #define GPE0_DW3_02 98 103 #define GPE0_DW3_03 99 104 #define GPE0_DW3_04 100 105 #define GPE0_DW3_05 101 106 #define GPE0_DW3_06 102 107 #define GPE0_DW3_07 103 108 #define GPE0_DW3_08 104 109 #define GPE0_DW3_09 105 110 #define GPE0_DW3_10 106 111 #define GPE0_DW3_11 107 112 #define GPE0_DW3_12 108 113 #define GPE0_DW3_13 109 114 #define GPE0_DW3_14 110 115 #define GPE0_DW3_15 111 116 #define GPE0_DW3_16 112 117 #define GPE0_DW3_17 113 118 #define GPE0_DW3_18 114 119 #define GPE0_DW3_19 115 120 #define GPE0_DW3_20 116 121 #define GPE0_DW3_21 117 122 #define GPE0_DW3_22 118 123 #define GPE0_DW3_23 119 124 #define GPE0_DW3_24 120 125 #define GPE0_DW3_25 121 126 #define GPE0_DW3_26 122 127 #define GPE0_DW3_27 123 128 #define GPE0_DW3_28 124 129 #define GPE0_DW3_29 125 130 #define GPE0_DW3_30 126 131 #define GPE0_DW3_31 127 132 133 #define GPE_MAX GPE0_DW3_31 134 135 #endif 136