1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2011 The Chromium OS Authors.
4  */
5 
6 #ifndef __X86_CACHE_H__
7 #define __X86_CACHE_H__
8 
9 /*
10  * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
11  * use 64-bytes, a safe default for x86.
12  */
13 #ifndef CONFIG_SYS_CACHELINE_SIZE
14 #define CONFIG_SYS_CACHELINE_SIZE	64
15 #endif
16 
17 #define ARCH_DMA_MINALIGN		CONFIG_SYS_CACHELINE_SIZE
18 
wbinvd(void)19 static inline void wbinvd(void)
20 {
21 	asm volatile ("wbinvd" : : : "memory");
22 }
23 
invd(void)24 static inline void invd(void)
25 {
26 	asm volatile("invd" : : : "memory");
27 }
28 
29 /* Enable caches and write buffer */
30 void enable_caches(void);
31 
32 /* Disable caches and write buffer */
33 void disable_caches(void);
34 
35 #endif /* __X86_CACHE_H__ */
36