1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <handoff.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/fsp/fsp_support.h>
11 #include <asm/e820.h>
12 #include <asm/global_data.h>
13 #include <asm/mrccache.h>
14 #include <asm/mtrr.h>
15 #include <asm/post.h>
16 #include <dm/ofnode.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
fsp_scan_for_ram_size(void)20 int fsp_scan_for_ram_size(void)
21 {
22 phys_size_t ram_size = 0;
23 const struct hob_header *hdr;
24 struct hob_res_desc *res_desc;
25
26 hdr = gd->arch.hob_list;
27 while (!end_of_hob(hdr)) {
28 if (hdr->type == HOB_TYPE_RES_DESC) {
29 res_desc = (struct hob_res_desc *)hdr;
30 if (res_desc->type == RES_SYS_MEM ||
31 res_desc->type == RES_MEM_RESERVED)
32 ram_size += res_desc->len;
33 }
34 hdr = get_next_hob(hdr);
35 }
36
37 gd->ram_size = ram_size;
38 post_code(POST_DRAM);
39
40 return 0;
41 };
42
dram_init_banksize(void)43 int dram_init_banksize(void)
44 {
45 efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
46 const struct hob_header *hdr;
47 struct hob_res_desc *res_desc;
48 phys_addr_t mtrr_top;
49 phys_addr_t low_end;
50 uint bank;
51
52 if (!ll_boot_init()) {
53 gd->bd->bi_dram[0].start = 0;
54 gd->bd->bi_dram[0].size = gd->ram_size;
55
56 mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
57 return 0;
58 }
59
60 low_end = 0; /* top of low memory usable by U-Boot */
61 mtrr_top = 0; /* top of low memory (even if reserved) */
62 for (bank = 1, hdr = gd->arch.hob_list;
63 bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
64 hdr = get_next_hob(hdr)) {
65 if (hdr->type != HOB_TYPE_RES_DESC)
66 continue;
67 res_desc = (struct hob_res_desc *)hdr;
68 if (!guidcmp(&res_desc->owner, &fsp))
69 low_end = res_desc->phys_start;
70 if (res_desc->type != RES_SYS_MEM &&
71 res_desc->type != RES_MEM_RESERVED)
72 continue;
73 if (res_desc->phys_start < (1ULL << 32)) {
74 mtrr_top = max(mtrr_top,
75 res_desc->phys_start + res_desc->len);
76 } else {
77 gd->bd->bi_dram[bank].start = res_desc->phys_start;
78 gd->bd->bi_dram[bank].size = res_desc->len;
79 mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
80 res_desc->len);
81 log_debug("ram %llx %llx\n",
82 gd->bd->bi_dram[bank].start,
83 gd->bd->bi_dram[bank].size);
84 }
85 }
86
87 /* Add the memory below 4GB */
88 gd->bd->bi_dram[0].start = 0;
89 gd->bd->bi_dram[0].size = low_end;
90
91 /*
92 * Set up an MTRR to the top of low, reserved memory. This is necessary
93 * for graphics to run at full speed in U-Boot.
94 */
95 mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
96
97 return 0;
98 }
99
install_e820_map(unsigned int max_entries,struct e820_entry * entries)100 unsigned int install_e820_map(unsigned int max_entries,
101 struct e820_entry *entries)
102 {
103 unsigned int num_entries = 0;
104 const struct hob_header *hdr;
105 struct hob_res_desc *res_desc;
106 const fdt64_t *prop;
107 int size;
108
109 hdr = gd->arch.hob_list;
110
111 while (!end_of_hob(hdr)) {
112 if (hdr->type == HOB_TYPE_RES_DESC) {
113 res_desc = (struct hob_res_desc *)hdr;
114 entries[num_entries].addr = res_desc->phys_start;
115 entries[num_entries].size = res_desc->len;
116
117 if (res_desc->type == RES_SYS_MEM)
118 entries[num_entries].type = E820_RAM;
119 else if (res_desc->type == RES_MEM_RESERVED)
120 entries[num_entries].type = E820_RESERVED;
121
122 num_entries++;
123 }
124 hdr = get_next_hob(hdr);
125 }
126
127 /* Mark PCIe ECAM address range as reserved */
128 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
129 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
130 entries[num_entries].type = E820_RESERVED;
131 num_entries++;
132
133 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
134 ulong stack_size;
135
136 stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME,
137 (CONFIG_STACK_SIZE_RESUME), (0));
138 /*
139 * Everything between U-Boot's stack and ram top needs to be
140 * reserved in order for ACPI S3 resume to work.
141 */
142 entries[num_entries].addr = gd->start_addr_sp - stack_size;
143 entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
144 stack_size;
145 entries[num_entries].type = E820_RESERVED;
146 num_entries++;
147 }
148
149 prop = ofnode_read_chosen_prop("e820-entries", &size);
150 if (prop) {
151 int count = size / (sizeof(u64) * 3);
152 int i;
153
154 if (num_entries + count >= max_entries)
155 return -ENOSPC;
156 for (i = 0; i < count; i++, num_entries++, prop += 3) {
157 entries[num_entries].addr = fdt64_to_cpu(prop[0]);
158 entries[num_entries].size = fdt64_to_cpu(prop[1]);
159 entries[num_entries].type = fdt64_to_cpu(prop[2]);
160 }
161 }
162
163 return num_entries;
164 }
165
166 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
handoff_arch_save(struct spl_handoff * ho)167 int handoff_arch_save(struct spl_handoff *ho)
168 {
169 ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
170 ho->arch.hob_list = gd->arch.hob_list;
171
172 return 0;
173 }
174 #endif
175