1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <init.h>
10 #include <log.h>
11 #include <malloc.h>
12 #include <rtc.h>
13 #include <acpi/acpi_s3.h>
14 #include <asm/cmos_layout.h>
15 #include <asm/early_cmos.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/mrccache.h>
19 #include <asm/post.h>
20 #include <asm/processor.h>
21 #include <asm/fsp1/fsp_support.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
fsp_prepare_mrc_cache(void)25 static void *fsp_prepare_mrc_cache(void)
26 {
27 struct mrc_data_container *cache;
28 struct mrc_region entry;
29 int ret;
30
31 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
32 if (ret)
33 return NULL;
34
35 cache = mrccache_find_current(&entry);
36 if (!cache)
37 return NULL;
38
39 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
40 cache->data, cache->data_size, cache->checksum);
41
42 return cache->data;
43 }
44
arch_fsp_init(void)45 int arch_fsp_init(void)
46 {
47 void *nvs;
48 int stack = CONFIG_FSP_TEMP_RAM_ADDR;
49 int boot_mode = BOOT_FULL_CONFIG;
50 int prev_sleep_state;
51
52 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
53 prev_sleep_state = chipset_prev_sleep_state();
54 gd->arch.prev_sleep_state = prev_sleep_state;
55 }
56
57 if (!gd->arch.hob_list) {
58 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
59 nvs = fsp_prepare_mrc_cache();
60 else
61 nvs = NULL;
62
63 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
64 prev_sleep_state == ACPI_S3) {
65 if (nvs == NULL) {
66 /* If waking from S3 and no cache then */
67 debug("No MRC cache found in S3 resume path\n");
68 post_code(POST_RESUME_FAILURE);
69 /* Clear Sleep Type */
70 chipset_clear_sleep_state();
71 /* Reboot */
72 debug("Rebooting..\n");
73 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
74 /* Should not reach here.. */
75 panic("Reboot System");
76 }
77
78 /*
79 * DM is not available yet at this point, hence call
80 * CMOS access library which does not depend on DM.
81 */
82 stack = cmos_read32(CMOS_FSP_STACK_ADDR);
83 boot_mode = BOOT_ON_S3_RESUME;
84 }
85
86 /*
87 * The first time we enter here, call fsp_init().
88 * Note the execution does not return to this function,
89 * instead it jumps to fsp_continue().
90 */
91 fsp_init(stack, boot_mode, nvs);
92 } else {
93 /*
94 * The second time we enter here, adjust the size of malloc()
95 * pool before relocation. Given gd->malloc_base was adjusted
96 * after the call to board_init_f_init_reserve() in arch/x86/
97 * cpu/start.S, we should fix up gd->malloc_limit here.
98 */
99 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
100 }
101
102 return 0;
103 }
104