1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Google, Inc
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <log.h>
11 #include <pch.h>
12 #include <pci.h>
13 #include <asm/cpu.h>
14 #include <asm/global_data.h>
15 #include <asm/gpio.h>
16 #include <asm/io.h>
17 #include <asm/pci.h>
18 #include <dm/pinctrl.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #define GPIO_USESEL_OFFSET(x) (x)
23 #define GPIO_IOSEL_OFFSET(x) (x + 4)
24 #define GPIO_LVL_OFFSET(x) ((x) ? (x) + 8 : 0xc)
25 #define GPI_INV 0x2c
26
27 #define IOPAD_MODE_MASK 0x7
28 #define IOPAD_PULL_ASSIGN_SHIFT 7
29 #define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
30 #define IOPAD_PULL_STRENGTH_SHIFT 9
31 #define IOPAD_PULL_STRENGTH_MASK (0x3 << IOPAD_PULL_STRENGTH_SHIFT)
32
ich6_pinctrl_set_value(uint16_t base,unsigned offset,int value)33 static int ich6_pinctrl_set_value(uint16_t base, unsigned offset, int value)
34 {
35 if (value)
36 setio_32(base, 1UL << offset);
37 else
38 clrio_32(base, 1UL << offset);
39
40 return 0;
41 }
42
ich6_pinctrl_set_function(uint16_t base,unsigned offset,int func)43 static int ich6_pinctrl_set_function(uint16_t base, unsigned offset, int func)
44 {
45 if (func)
46 setio_32(base, 1UL << offset);
47 else
48 clrio_32(base, 1UL << offset);
49
50 return 0;
51 }
52
ich6_pinctrl_set_direction(uint16_t base,unsigned offset,int dir)53 static int ich6_pinctrl_set_direction(uint16_t base, unsigned offset, int dir)
54 {
55 if (!dir)
56 setio_32(base, 1UL << offset);
57 else
58 clrio_32(base, 1UL << offset);
59
60 return 0;
61 }
62
ich6_pinctrl_cfg_pin(s32 gpiobase,s32 iobase,int pin_node)63 static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
64 {
65 bool is_gpio, invert;
66 u32 gpio_offset[2];
67 int pad_offset;
68 int dir, val;
69 int ret;
70
71 /*
72 * GPIO node is not mandatory, so we only do the pinmuxing if the
73 * node exists.
74 */
75 ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
76 gpio_offset, 2);
77 if (!ret) {
78 /* Do we want to force the GPIO mode? */
79 is_gpio = fdtdec_get_bool(gd->fdt_blob, pin_node, "mode-gpio");
80 if (is_gpio)
81 ich6_pinctrl_set_function(GPIO_USESEL_OFFSET(gpiobase) +
82 gpio_offset[0], gpio_offset[1],
83 1);
84
85 dir = fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
86 if (dir != -1)
87 ich6_pinctrl_set_direction(GPIO_IOSEL_OFFSET(gpiobase) +
88 gpio_offset[0], gpio_offset[1],
89 dir);
90
91 val = fdtdec_get_int(gd->fdt_blob, pin_node, "output-value",
92 -1);
93 if (val != -1)
94 ich6_pinctrl_set_value(GPIO_LVL_OFFSET(gpiobase) +
95 gpio_offset[0], gpio_offset[1],
96 val);
97
98 invert = fdtdec_get_bool(gd->fdt_blob, pin_node, "invert");
99 if (invert)
100 setio_32(gpiobase + GPI_INV, 1 << gpio_offset[1]);
101 debug("gpio %#x bit %d, is_gpio %d, dir %d, val %d, invert %d\n",
102 gpio_offset[0], gpio_offset[1], is_gpio, dir, val,
103 invert);
104 }
105
106 /* if iobase is present, let's configure the pad */
107 if (iobase != -1) {
108 ulong iobase_addr;
109
110 /*
111 * The offset for the same pin for the IOBASE and GPIOBASE are
112 * different, so instead of maintaining a lookup table,
113 * the device tree should provide directly the correct
114 * value for both mapping.
115 */
116 pad_offset = fdtdec_get_int(gd->fdt_blob, pin_node,
117 "pad-offset", -1);
118 if (pad_offset == -1)
119 return 0;
120
121 /* compute the absolute pad address */
122 iobase_addr = iobase + pad_offset;
123
124 /*
125 * Do we need to set a specific function mode?
126 * If someone put also 'mode-gpio', this option will
127 * be just ignored by the controller
128 */
129 val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
130 if (val != -1)
131 clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
132
133 /* Configure the pull-up/down if needed */
134 val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
135 if (val != -1)
136 clrsetbits_le32(iobase_addr,
137 IOPAD_PULL_ASSIGN_MASK,
138 val << IOPAD_PULL_ASSIGN_SHIFT);
139
140 val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength",
141 -1);
142 if (val != -1)
143 clrsetbits_le32(iobase_addr,
144 IOPAD_PULL_STRENGTH_MASK,
145 val << IOPAD_PULL_STRENGTH_SHIFT);
146
147 debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
148 readl(iobase_addr));
149 }
150
151 return 0;
152 }
153
ich6_pinctrl_probe(struct udevice * dev)154 static int ich6_pinctrl_probe(struct udevice *dev)
155 {
156 struct udevice *pch;
157 int pin_node;
158 int ret;
159 u32 gpiobase;
160 u32 iobase = -1;
161
162 debug("%s: start\n", __func__);
163 ret = uclass_first_device(UCLASS_PCH, &pch);
164 if (ret)
165 return ret;
166 if (!pch)
167 return -ENODEV;
168
169 /*
170 * Get the memory/io base address to configure every pins.
171 * IOBASE is used to configure the mode/pads
172 * GPIOBASE is used to configure the direction and default value
173 */
174 ret = pch_get_gpio_base(pch, &gpiobase);
175 if (ret) {
176 debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
177 gpiobase);
178 return -EINVAL;
179 }
180
181 /*
182 * Get the IOBASE, this is not mandatory as this is not
183 * supported by all the CPU
184 */
185 ret = pch_get_io_base(pch, &iobase);
186 if (ret && ret != -ENOSYS) {
187 debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase);
188 return -EINVAL;
189 }
190
191 for (pin_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
192 pin_node > 0;
193 pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
194 /* Configure the pin */
195 ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
196 if (ret != 0) {
197 debug("%s: invalid configuration for the pin %d\n",
198 __func__, pin_node);
199 return ret;
200 }
201 }
202 debug("%s: done\n", __func__);
203
204 return 0;
205 }
206
207 static const struct udevice_id ich6_pinctrl_match[] = {
208 { .compatible = "intel,x86-pinctrl", .data = X86_SYSCON_PINCONF },
209 { /* sentinel */ }
210 };
211
212 U_BOOT_DRIVER(ich6_pinctrl) = {
213 .name = "ich6_pinctrl",
214 .id = UCLASS_SYSCON,
215 .of_match = ich6_pinctrl_match,
216 .probe = ich6_pinctrl_probe,
217 };
218