1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 *
5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 *
7 * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
8 */
9
10 #include <common.h>
11 #include <init.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <env.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/iomux-mx35.h>
20 #include <i2c.h>
21 #include <linux/types.h>
22 #include <asm/gpio.h>
23 #include <asm/arch/sys_proto.h>
24 #include <netdev.h>
25 #include <fdt_support.h>
26 #include <mtd_node.h>
27 #include <jffs2/load_kernel.h>
28
29 #ifndef CONFIG_BOARD_EARLY_INIT_F
30 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
31 #endif
32
33 #define CCM_CCMR_CONFIG 0x003F4208
34
35 #define ESDCTL_DDR2_CONFIG 0x007FFC3F
36
dram_wait(unsigned int count)37 static inline void dram_wait(unsigned int count)
38 {
39 volatile unsigned int wait = count;
40
41 while (wait--)
42 ;
43 }
44
45 DECLARE_GLOBAL_DATA_PTR;
46
dram_init(void)47 int dram_init(void)
48 {
49 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
50 PHYS_SDRAM_1_SIZE);
51
52 return 0;
53 }
54
board_setup_sdram(void)55 static void board_setup_sdram(void)
56 {
57 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
58
59 /* Initialize with default values both CSD0/1 */
60 writel(0x2000, &esdc->esdctl0);
61 writel(0x2000, &esdc->esdctl1);
62
63
64 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
65 13, 10, 2, 0x8080);
66 }
67
setup_iomux_uart3(void)68 static void setup_iomux_uart3(void)
69 {
70 static const iomux_v3_cfg_t uart3_pads[] = {
71 MX35_PAD_RTS2__UART3_RXD_MUX,
72 MX35_PAD_CTS2__UART3_TXD_MUX,
73 };
74
75 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
76 }
77
78 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
79
setup_iomux_i2c(void)80 static void setup_iomux_i2c(void)
81 {
82 static const iomux_v3_cfg_t i2c_pads[] = {
83 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
84 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
85
86 NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
87 NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
88 };
89
90 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
91 }
92
93
setup_iomux_spi(void)94 static void setup_iomux_spi(void)
95 {
96 static const iomux_v3_cfg_t spi_pads[] = {
97 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
98 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
99 MX35_PAD_CSPI1_SS0__CSPI1_SS0,
100 MX35_PAD_CSPI1_SS1__CSPI1_SS1,
101 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
102 };
103
104 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
105 }
106
setup_iomux_fec(void)107 static void setup_iomux_fec(void)
108 {
109 static const iomux_v3_cfg_t fec_pads[] = {
110 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
111 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
112 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
113 MX35_PAD_FEC_COL__FEC_COL,
114 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
115 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
116 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
117 MX35_PAD_FEC_MDC__FEC_MDC,
118 MX35_PAD_FEC_MDIO__FEC_MDIO,
119 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
120 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
121 MX35_PAD_FEC_CRS__FEC_CRS,
122 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
123 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
124 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
125 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
126 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
127 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
128 /* GPIO used to power off ethernet */
129 MX35_PAD_STXFS4__GPIO2_31,
130 };
131
132 /* setup pins for FEC */
133 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
134 }
135
board_early_init_f(void)136 int board_early_init_f(void)
137 {
138 struct ccm_regs *ccm =
139 (struct ccm_regs *)IMX_CCM_BASE;
140
141 /* setup GPIO3_1 to set HighVCore signal */
142 imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
143 gpio_direction_output(65, 1);
144
145 /* initialize PLL and clock configuration */
146 writel(CCM_CCMR_CONFIG, &ccm->ccmr);
147
148 writel(CCM_MPLL_532_HZ, &ccm->mpctl);
149 writel(CCM_PPLL_300_HZ, &ccm->ppctl);
150
151 /* Set the core to run at 532 Mhz */
152 writel(0x00001000, &ccm->pdr0);
153
154 /* Set-up RAM */
155 board_setup_sdram();
156
157 /* enable clocks */
158 writel(readl(&ccm->cgr0) |
159 MXC_CCM_CGR0_EMI_MASK |
160 MXC_CCM_CGR0_EDIO_MASK |
161 MXC_CCM_CGR0_EPIT1_MASK,
162 &ccm->cgr0);
163
164 writel(readl(&ccm->cgr1) |
165 MXC_CCM_CGR1_FEC_MASK |
166 MXC_CCM_CGR1_GPIO1_MASK |
167 MXC_CCM_CGR1_GPIO2_MASK |
168 MXC_CCM_CGR1_GPIO3_MASK |
169 MXC_CCM_CGR1_I2C1_MASK |
170 MXC_CCM_CGR1_I2C2_MASK |
171 MXC_CCM_CGR1_I2C3_MASK,
172 &ccm->cgr1);
173
174 /* Set-up NAND */
175 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
176
177 /* Set pinmux for the required peripherals */
178 setup_iomux_uart3();
179 setup_iomux_i2c();
180 setup_iomux_fec();
181 setup_iomux_spi();
182
183 return 0;
184 }
185
board_init(void)186 int board_init(void)
187 {
188 /* address of boot parameters */
189 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
190
191 /* Enable power for ethernet */
192 gpio_direction_output(63, 0);
193
194 udelay(2000);
195
196 return 0;
197 }
198
get_board_rev(void)199 u32 get_board_rev(void)
200 {
201 int rev = 0;
202
203 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
204 }
205
206 /*
207 * called prior to booting kernel or by 'fdt boardsetup' command
208 *
209 */
ft_board_setup(void * blob,struct bd_info * bd)210 int ft_board_setup(void *blob, struct bd_info *bd)
211 {
212 static const struct node_info nodes[] = {
213 { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
214 { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
215 };
216
217 if (env_get("fdt_noauto")) {
218 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
219 return 0;
220 }
221
222 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
223
224 return 0;
225 }
226