1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <miiphy.h>
9 #include <net.h>
10 #include <netdev.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <linux/bitops.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /*
20 * Those values and defines are taken from the Marvell U-Boot version
21 * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
22 */
23 #define DB_88F6720_MPP0_7 0x00020020 /* SPI */
24 #define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
25 #define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
26 #define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
27 #define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
28 #define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
29 #define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
30 #define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
31 #define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
32
33 #define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
34 #define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
35 #define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
36 #define DB_88F6720_GPP_OUT_VAL_LOW 0x0
37 #define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
38 #define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
39 #define DB_88F6720_GPP_POL_LOW 0x0
40 #define DB_88F6720_GPP_POL_MID 0x0
41 #define DB_88F6720_GPP_POL_HIGH 0x0
42
board_early_init_f(void)43 int board_early_init_f(void)
44 {
45 /* Configure MPP */
46 writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
47 writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
48 writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
49 writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
50 writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
51 writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
52 writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
53 writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
54 writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
55
56 /* Configure GPIO */
57 /* Set GPP Out value */
58 writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
59 writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
60 writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
61
62 /* Set GPP Polarity */
63 writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
64 writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
65 writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
66
67 /* Set GPP Out Enable */
68 writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
69 writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
70 writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
71
72 return 0;
73 }
74
board_init(void)75 int board_init(void)
76 {
77 /* adress of boot parameters */
78 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
79
80 return 0;
81 }
82
checkboard(void)83 int checkboard(void)
84 {
85 puts("Board: Marvell DB-88F6720\n");
86
87 return 0;
88 }
89
board_eth_init(struct bd_info * bis)90 int board_eth_init(struct bd_info *bis)
91 {
92 cpu_eth_init(bis); /* Built in controller(s) come first */
93 return pci_eth_init(bis);
94 }
95