1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <miiphy.h>
9 #include <net.h>
10 #include <netdev.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <linux/bitops.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define ETH_PHY_CTRL_REG 0
20 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
21 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
22
23 /*
24 * Those values and defines are taken from the Marvell U-Boot version
25 * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
26 * "RD-AXP-GP rev 1.0".
27 *
28 * GPPs
29 * MPP# NAME IN/OUT
30 * ----------------------------------------------
31 * 21 SW_Reset_ OUT
32 * 25 Phy_Int# IN
33 * 28 SDI_WP IN
34 * 29 SDI_Status IN
35 * 54-61 On GPP Connector ?
36 * 62 Switch Interrupt IN
37 * 63-65 Reserved from SW Board ?
38 * 66 SW_BRD connected IN
39 */
40 #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
41 #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
42 #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
43
44 #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
45 #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
46 #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
47
board_early_init_f(void)48 int board_early_init_f(void)
49 {
50 /* Configure MPP */
51 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
52 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
53 writel(0x33000000, MVEBU_MPP_BASE + 0x08);
54 writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
55 writel(0x11111111, MVEBU_MPP_BASE + 0x10);
56 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
57 writel(0x00000003, MVEBU_MPP_BASE + 0x18);
58 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
59 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
60
61 /* Configure GPIO */
62 writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
63 writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
64 writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
65 writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
66 writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
67 writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
68
69 return 0;
70 }
71
board_init(void)72 int board_init(void)
73 {
74 /* adress of boot parameters */
75 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
76
77 return 0;
78 }
79
checkboard(void)80 int checkboard(void)
81 {
82 puts("Board: Marvell DB-MV784MP-GP\n");
83
84 return 0;
85 }
86
board_eth_init(struct bd_info * bis)87 int board_eth_init(struct bd_info *bis)
88 {
89 cpu_eth_init(bis); /* Built in controller(s) come first */
90 return pci_eth_init(bis);
91 }
92
board_phy_config(struct phy_device * phydev)93 int board_phy_config(struct phy_device *phydev)
94 {
95 u16 reg;
96
97 /* Enable QSGMII AN */
98 /* Set page to 4 */
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
100 /* Enable AN */
101 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
102 /* Set page to 0 */
103 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
104
105 /* Phy C_ANEG */
106 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
107 reg |= 0x1E0;
108 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
109
110 /* Soft-Reset */
111 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
112 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
113
114 /* Power up the phy */
115 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
116 reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
117 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
118
119 printf("88E1545 Initialized\n");
120 return 0;
121 }
122