1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011
4 * eInfochips Ltd. <www.einfochips.com>
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
6 *
7 * Based on Aspenite:
8 * (C) Copyright 2010
9 * Marvell Semiconductor <www.marvell.com>
10 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 * Contributor: Mahavir Jain <mjain@marvell.com>
12 */
13
14 #include <common.h>
15 #include <init.h>
16 #include <log.h>
17 #include <mvmfp.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/mfp.h>
20 #include <asm/arch/armada100.h>
21 #include <asm/global_data.h>
22 #include <asm/gpio.h>
23 #include <miiphy.h>
24 #include <asm/mach-types.h>
25 #include <linux/delay.h>
26
27 #ifdef CONFIG_ARMADA100_FEC
28 #include <net.h>
29 #include <netdev.h>
30 #endif /* CONFIG_ARMADA100_FEC */
31
32 DECLARE_GLOBAL_DATA_PTR;
33
board_early_init_f(void)34 int board_early_init_f(void)
35 {
36 u32 mfp_cfg[] = {
37 /* I2C */
38 MFP105_CI2C_SDA,
39 MFP106_CI2C_SCL,
40
41 /* Enable Console on UART3 */
42 MFPO8_UART3_TXD,
43 MFPO9_UART3_RXD,
44
45 /* Ethernet PHY Interface */
46 MFP086_ETH_TXCLK,
47 MFP087_ETH_TXEN,
48 MFP088_ETH_TXDQ3,
49 MFP089_ETH_TXDQ2,
50 MFP090_ETH_TXDQ1,
51 MFP091_ETH_TXDQ0,
52 MFP092_ETH_CRS,
53 MFP093_ETH_COL,
54 MFP094_ETH_RXCLK,
55 MFP095_ETH_RXER,
56 MFP096_ETH_RXDQ3,
57 MFP097_ETH_RXDQ2,
58 MFP098_ETH_RXDQ1,
59 MFP099_ETH_RXDQ0,
60 MFP100_ETH_MDC,
61 MFP101_ETH_MDIO,
62 MFP103_ETH_RXDV,
63
64 /* SSP2 */
65 MFP107_SSP2_RXD,
66 MFP108_SSP2_TXD,
67 MFP110_SSP2_CS,
68 MFP111_SSP2_CLK,
69
70 MFP_EOC /*End of configuration*/
71 };
72 /* configure MFP's */
73 mfp_config(mfp_cfg);
74 return 0;
75 }
76
board_init(void)77 int board_init(void)
78 {
79 struct armd1apb2_registers *apb2_regs =
80 (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
81
82 /* arch number of Board */
83 gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
84 /* adress of boot parameters */
85 gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
86 /* Assert PHY_RST# */
87 gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
88 udelay(10);
89 /* Deassert PHY_RST# */
90 gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
91
92 /* Enable SSP2 clock */
93 writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
94 return 0;
95 }
96
97 #ifdef CONFIG_ARMADA100_FEC
board_eth_init(struct bd_info * bis)98 int board_eth_init(struct bd_info *bis)
99 {
100 struct armd1apmu_registers *apmu_regs =
101 (struct armd1apmu_registers *)ARMD1_APMU_BASE;
102
103 /* Enable clock of ethernet controller */
104 writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
105
106 return armada100_fec_register(ARMD1_FEC_BASE);
107 }
108
109 #ifdef CONFIG_RESET_PHY_R
110 /* Configure and initialize PHY chip 88E3015 */
reset_phy(void)111 void reset_phy(void)
112 {
113 u16 phy_adr;
114 const char *name = "armd-fec0";
115
116 if (miiphy_set_current_dev(name))
117 return;
118
119 /* command to read PHY dev address */
120 if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
121 printf("Err..%s could not read PHY dev address\n", __func__);
122 return;
123 }
124
125 /* Set Ethernet LED in TX blink mode */
126 miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
127 miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
128
129 /* reset the phy */
130 miiphy_reset(name, phy_adr);
131 debug("88E3015 Initialized on %s\n", name);
132 }
133 #endif /* CONFIG_RESET_PHY_R */
134 #endif /* CONFIG_ARMADA100_FEC */
135