1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
4 *
5 * Based on sheevaplug.c originally written by
6 * Prafulla Wadaskar <prafulla@marvell.com>
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
9 */
10
11 #include <common.h>
12 #include <bootstage.h>
13 #include <init.h>
14 #include <miiphy.h>
15 #include <net.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch/mpp.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/global_data.h>
20 #include <asm/io.h>
21 #include <asm/mach-types.h>
22 #include "dockstar.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
board_early_init_f(void)26 int board_early_init_f(void)
27 {
28 /*
29 * default gpio configuration
30 * There are maximum 64 gpios controlled through 2 sets of registers
31 * the below configuration configures mainly initial LED status
32 */
33 mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
34 DOCKSTAR_OE_VAL_HIGH,
35 DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
36
37 /* Multi-Purpose Pins Functionality configuration */
38 static const u32 kwmpp_config[] = {
39 MPP0_NF_IO2,
40 MPP1_NF_IO3,
41 MPP2_NF_IO4,
42 MPP3_NF_IO5,
43 MPP4_NF_IO6,
44 MPP5_NF_IO7,
45 MPP6_SYSRST_OUTn,
46 MPP7_GPO,
47 MPP8_UART0_RTS,
48 MPP9_UART0_CTS,
49 MPP10_UART0_TXD,
50 MPP11_UART0_RXD,
51 MPP12_SD_CLK,
52 MPP13_SD_CMD,
53 MPP14_SD_D0,
54 MPP15_SD_D1,
55 MPP16_SD_D2,
56 MPP17_SD_D3,
57 MPP18_NF_IO0,
58 MPP19_NF_IO1,
59 MPP20_GPIO,
60 MPP21_GPIO,
61 MPP22_GPIO,
62 MPP23_GPIO,
63 MPP24_GPIO,
64 MPP25_GPIO,
65 MPP26_GPIO,
66 MPP27_GPIO,
67 MPP28_GPIO,
68 MPP29_TSMP9,
69 MPP30_GPIO,
70 MPP31_GPIO,
71 MPP32_GPIO,
72 MPP33_GPIO,
73 MPP34_GPIO,
74 MPP35_GPIO,
75 MPP36_GPIO,
76 MPP37_GPIO,
77 MPP38_GPIO,
78 MPP39_GPIO,
79 MPP40_GPIO,
80 MPP41_GPIO,
81 MPP42_GPIO,
82 MPP43_GPIO,
83 MPP44_GPIO,
84 MPP45_GPIO,
85 MPP46_GPIO,
86 MPP47_GPIO,
87 MPP48_GPIO,
88 MPP49_GPIO,
89 0
90 };
91 kirkwood_mpp_conf(kwmpp_config, NULL);
92 return 0;
93 }
94
board_init(void)95 int board_init(void)
96 {
97 /*
98 * arch number of board
99 */
100 gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
101
102 /* address of boot parameters */
103 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
104
105 return 0;
106 }
107
108 #ifdef CONFIG_RESET_PHY_R
109 /* Configure and enable MV88E1116 PHY */
reset_phy(void)110 void reset_phy(void)
111 {
112 u16 reg;
113 u16 devadr;
114 char *name = "egiga0";
115
116 if (miiphy_set_current_dev(name))
117 return;
118
119 /* command to read PHY dev address */
120 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
121 printf("Err..%s could not read PHY dev address\n",
122 __FUNCTION__);
123 return;
124 }
125
126 /*
127 * Enable RGMII delay on Tx and Rx for CPU port
128 * Ref: sec 4.7.2 of chip datasheet
129 */
130 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
131 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
132 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
133 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
134 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
135
136 /* reset the phy */
137 miiphy_reset(name, devadr);
138
139 printf("88E1116 Initialized on %s\n", name);
140 }
141 #endif /* CONFIG_RESET_PHY_R */
142
143 #define GREEN_LED (1 << 14)
144 #define ORANGE_LED (1 << 15)
145 #define BOTH_LEDS (GREEN_LED | ORANGE_LED)
146 #define NEITHER_LED 0
147
set_leds(u32 leds,u32 blinking)148 static void set_leds(u32 leds, u32 blinking)
149 {
150 struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
151 u32 oe = readl(&r->oe) | BOTH_LEDS;
152 writel(oe & ~leds, &r->oe); /* active low */
153 u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
154 writel(bl | blinking, &r->blink_en);
155 }
156
show_boot_progress(int val)157 void show_boot_progress(int val)
158 {
159 switch (val) {
160 case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
161 set_leds(BOTH_LEDS, NEITHER_LED);
162 break;
163 case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
164 set_leds(GREEN_LED, GREEN_LED);
165 break;
166 default:
167 if (val < 0) /* error */
168 set_leds(ORANGE_LED, ORANGE_LED);
169 break;
170 }
171 }
172