1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Timesys Corporation
4 * Copyright 2016 Advantech Corporation
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 */
7
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/global_data.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <asm/gpio.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/video.h>
22 #include <mmc.h>
23 #include <fsl_esdhc_imx.h>
24 #include <miiphy.h>
25 #include <netdev.h>
26 #include <asm/arch/mxc_hdmi.h>
27 #include <asm/arch/crm_regs.h>
28 #include <asm/io.h>
29 #include <asm/arch/sys_proto.h>
30 #include <i2c.h>
31 #include <input.h>
32 #include <pwm.h>
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_HYS)
38
39 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
45 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
48 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
49
50 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
51 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
52
53 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
55
56 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
58
59 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
61 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
62
63 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
64
dram_init(void)65 int dram_init(void)
66 {
67 gd->ram_size = imx_ddr_size();
68
69 return 0;
70 }
71
72 static iomux_v3_cfg_t const uart3_pads[] = {
73 MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
75 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
76 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77 };
78
79 static iomux_v3_cfg_t const uart4_pads[] = {
80 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
81 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 };
83
84 static iomux_v3_cfg_t const enet_pads[] = {
85 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
94 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
95 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
96 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
97 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
98 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
99 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
100 /* AR8033 PHY Reset */
101 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 };
103
setup_iomux_enet(void)104 static void setup_iomux_enet(void)
105 {
106 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
107
108 /* Reset AR8033 PHY */
109 gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
110 mdelay(10);
111 gpio_set_value(IMX_GPIO_NR(1, 28), 1);
112 mdelay(1);
113 }
114
115 static iomux_v3_cfg_t const usdhc2_pads[] = {
116 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
123 };
124
125 static iomux_v3_cfg_t const usdhc3_pads[] = {
126 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 };
138
139 static iomux_v3_cfg_t const usdhc4_pads[] = {
140 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
151 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
152 };
153
154 static iomux_v3_cfg_t const ecspi1_pads[] = {
155 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
156 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
157 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
158 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
159 };
160
161 static struct i2c_pads_info i2c_pad_info1 = {
162 .scl = {
163 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
164 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
165 .gp = IMX_GPIO_NR(5, 27)
166 },
167 .sda = {
168 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
169 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
170 .gp = IMX_GPIO_NR(5, 26)
171 }
172 };
173
174 static struct i2c_pads_info i2c_pad_info2 = {
175 .scl = {
176 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
177 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
178 .gp = IMX_GPIO_NR(4, 12)
179 },
180 .sda = {
181 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
182 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
183 .gp = IMX_GPIO_NR(4, 13)
184 }
185 };
186
187 static struct i2c_pads_info i2c_pad_info3 = {
188 .scl = {
189 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
190 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
191 .gp = IMX_GPIO_NR(1, 3)
192 },
193 .sda = {
194 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
195 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
196 .gp = IMX_GPIO_NR(1, 6)
197 }
198 };
199
200 #ifdef CONFIG_MXC_SPI
board_spi_cs_gpio(unsigned bus,unsigned cs)201 int board_spi_cs_gpio(unsigned bus, unsigned cs)
202 {
203 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
204 }
205
setup_spi(void)206 static void setup_spi(void)
207 {
208 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
209 }
210 #endif
211
212 static iomux_v3_cfg_t const pcie_pads[] = {
213 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
214 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
215 };
216
setup_pcie(void)217 static void setup_pcie(void)
218 {
219 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
220 }
221
setup_iomux_uart(void)222 static void setup_iomux_uart(void)
223 {
224 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
225 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
226 }
227
228 #ifdef CONFIG_FSL_ESDHC_IMX
229 struct fsl_esdhc_cfg usdhc_cfg[3] = {
230 {USDHC2_BASE_ADDR},
231 {USDHC3_BASE_ADDR},
232 {USDHC4_BASE_ADDR},
233 };
234
235 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
236 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
237
board_mmc_getcd(struct mmc * mmc)238 int board_mmc_getcd(struct mmc *mmc)
239 {
240 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
241 int ret = 0;
242
243 switch (cfg->esdhc_base) {
244 case USDHC2_BASE_ADDR:
245 ret = !gpio_get_value(USDHC2_CD_GPIO);
246 break;
247 case USDHC3_BASE_ADDR:
248 ret = 1; /* eMMC is always present */
249 break;
250 case USDHC4_BASE_ADDR:
251 ret = !gpio_get_value(USDHC4_CD_GPIO);
252 break;
253 }
254
255 return ret;
256 }
257
board_mmc_init(struct bd_info * bis)258 int board_mmc_init(struct bd_info *bis)
259 {
260 int ret;
261 int i;
262
263 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
264 switch (i) {
265 case 0:
266 imx_iomux_v3_setup_multiple_pads(
267 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
268 gpio_direction_input(USDHC2_CD_GPIO);
269 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
270 break;
271 case 1:
272 imx_iomux_v3_setup_multiple_pads(
273 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
274 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
275 break;
276 case 2:
277 imx_iomux_v3_setup_multiple_pads(
278 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
279 gpio_direction_input(USDHC4_CD_GPIO);
280 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
281 break;
282 default:
283 printf("Warning: you configured more USDHC controllers\n"
284 "(%d) then supported by the board (%d)\n",
285 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
286 return -EINVAL;
287 }
288
289 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
290 if (ret)
291 return ret;
292 }
293
294 return 0;
295 }
296 #endif
297
mx6_rgmii_rework(struct phy_device * phydev)298 static int mx6_rgmii_rework(struct phy_device *phydev)
299 {
300 /* set device address 0x7 */
301 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
302 /* offset 0x8016: CLK_25M Clock Select */
303 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
304 /* enable register write, no post increment, address 0x7 */
305 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
306 /* set to 125 MHz from local PLL source */
307 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
308 /* set debug port address: SerDes Test and System Mode Control */
309 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
310 /* enable rgmii tx clock delay */
311 /* set the reserved bits to avoid board specific voltage peak issue*/
312 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
313
314 return 0;
315 }
316
board_phy_config(struct phy_device * phydev)317 int board_phy_config(struct phy_device *phydev)
318 {
319 mx6_rgmii_rework(phydev);
320
321 if (phydev->drv->config)
322 phydev->drv->config(phydev);
323
324 return 0;
325 }
326
327 #if defined(CONFIG_VIDEO_IPUV3)
328 static iomux_v3_cfg_t const backlight_pads[] = {
329 /* Power for LVDS Display */
330 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
331 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
332 /* Backlight enable for LVDS display */
333 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
334 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
335 /* backlight PWM brightness control */
336 MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
337 };
338
do_enable_hdmi(struct display_info_t const * dev)339 static void do_enable_hdmi(struct display_info_t const *dev)
340 {
341 imx_enable_hdmi_phy();
342 }
343
board_cfb_skip(void)344 int board_cfb_skip(void)
345 {
346 gpio_direction_output(LVDS_POWER_GP, 1);
347
348 return 0;
349 }
350
detect_baseboard(struct display_info_t const * dev)351 static int detect_baseboard(struct display_info_t const *dev)
352 {
353 return 0 == dev->addr;
354 }
355
356 struct display_info_t const displays[] = {{
357 .bus = -1,
358 .addr = 0,
359 .pixfmt = IPU_PIX_FMT_RGB24,
360 .detect = detect_baseboard,
361 .enable = NULL,
362 .mode = {
363 .name = "SHARP-LQ156M1LG21",
364 .refresh = 60,
365 .xres = 1920,
366 .yres = 1080,
367 .pixclock = 7851,
368 .left_margin = 100,
369 .right_margin = 40,
370 .upper_margin = 30,
371 .lower_margin = 3,
372 .hsync_len = 10,
373 .vsync_len = 2,
374 .sync = FB_SYNC_EXT,
375 .vmode = FB_VMODE_NONINTERLACED
376 } }, {
377 .bus = -1,
378 .addr = 3,
379 .pixfmt = IPU_PIX_FMT_RGB24,
380 .detect = detect_hdmi,
381 .enable = do_enable_hdmi,
382 .mode = {
383 .name = "HDMI",
384 .refresh = 60,
385 .xres = 1024,
386 .yres = 768,
387 .pixclock = 15385,
388 .left_margin = 220,
389 .right_margin = 40,
390 .upper_margin = 21,
391 .lower_margin = 7,
392 .hsync_len = 60,
393 .vsync_len = 10,
394 .sync = FB_SYNC_EXT,
395 .vmode = FB_VMODE_NONINTERLACED
396 } } };
397 size_t display_count = ARRAY_SIZE(displays);
398
setup_display(void)399 static void setup_display(void)
400 {
401 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
402 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
403
404 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
405
406 imx_setup_hdmi();
407
408 /* Set LDB_DI0 as clock source for IPU_DI0 */
409 clrsetbits_le32(&mxc_ccm->chsccdr,
410 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
411 (CHSCCDR_CLK_SEL_LDB_DI0 <<
412 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
413
414 /* Turn on IPU LDB DI0 clocks */
415 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
416
417 enable_ipu_clock();
418
419 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
420 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
421 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
422 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
423 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
424 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
425 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
426 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
427 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
428 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
429 &iomux->gpr[2]);
430
431 clrsetbits_le32(&iomux->gpr[3],
432 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
433 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
434 IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
435 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
436 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
437
438 /* backlights off until needed */
439 imx_iomux_v3_setup_multiple_pads(backlight_pads,
440 ARRAY_SIZE(backlight_pads));
441
442 gpio_direction_input(LVDS_POWER_GP);
443 gpio_direction_input(LVDS_BACKLIGHT_GP);
444 }
445 #endif /* CONFIG_VIDEO_IPUV3 */
446
447 /*
448 * Do not overwrite the console
449 * Use always serial for U-Boot console
450 */
overwrite_console(void)451 int overwrite_console(void)
452 {
453 return 1;
454 }
455
board_eth_init(struct bd_info * bis)456 int board_eth_init(struct bd_info *bis)
457 {
458 setup_iomux_enet();
459 setup_pcie();
460
461 return cpu_eth_init(bis);
462 }
463
464 static iomux_v3_cfg_t const misc_pads[] = {
465 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
466 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
467 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
468 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
469 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
470 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
471 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
472 };
473 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
474 #define WIFI_EN IMX_GPIO_NR(6, 14)
475
setup_ba16_sata(void)476 int setup_ba16_sata(void)
477 {
478 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
479 int ret;
480
481 ret = enable_sata_clock();
482 if (ret)
483 return ret;
484
485 clrsetbits_le32(&iomuxc_regs->gpr[13],
486 IOMUXC_GPR13_SATA_MASK,
487 IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
488 |IOMUXC_GPR13_SATA_PHY_7_SATA2M
489 |IOMUXC_GPR13_SATA_SPEED_3G
490 |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
491 |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
492 |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
493 |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
494 |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
495 |IOMUXC_GPR13_SATA_PHY_1_SLOW);
496
497 return 0;
498 }
499
board_early_init_f(void)500 int board_early_init_f(void)
501 {
502 imx_iomux_v3_setup_multiple_pads(misc_pads,
503 ARRAY_SIZE(misc_pads));
504
505 setup_iomux_uart();
506
507 #if defined(CONFIG_VIDEO_IPUV3)
508 /* Set LDB clock to PLL2 PFD0 */
509 select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
510 #endif
511 return 0;
512 }
513
board_init(void)514 int board_init(void)
515 {
516 gpio_direction_output(SUS_S3_OUT, 1);
517 gpio_direction_output(WIFI_EN, 1);
518 #if defined(CONFIG_VIDEO_IPUV3)
519 setup_display();
520 #endif
521 /* address of boot parameters */
522 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
523
524 #ifdef CONFIG_MXC_SPI
525 setup_spi();
526 #endif
527 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
528 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
529 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
530
531 return 0;
532 }
533
534 #ifdef CONFIG_CMD_BMODE
535 static const struct boot_mode board_boot_modes[] = {
536 /* 4 bit bus width */
537 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
538 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
539 {NULL, 0},
540 };
541 #endif
542
pmic_init(void)543 void pmic_init(void)
544 {
545
546 #define DA9063_ADDR 0x58
547 #define BCORE2_CONF 0x9D
548 #define BCORE1_CONF 0x9E
549 #define BPRO_CONF 0x9F
550 #define BIO_CONF 0xA0
551 #define BMEM_CONF 0xA1
552 #define BPERI_CONF 0xA2
553 #define MODE_BIT_H 7
554 #define MODE_BIT_L 6
555
556 uchar val;
557 i2c_set_bus_num(2);
558
559 i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
560 val |= (1 << MODE_BIT_H);
561 val &= ~(1 << MODE_BIT_L);
562 i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
563
564 i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
565 val |= (1 << MODE_BIT_H);
566 val &= ~(1 << MODE_BIT_L);
567 i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
568
569 i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
570 val |= (1 << MODE_BIT_H);
571 val &= ~(1 << MODE_BIT_L);
572 i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
573
574 i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
575 val |= (1 << MODE_BIT_H);
576 val &= ~(1 << MODE_BIT_L);
577 i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
578
579 i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
580 val |= (1 << MODE_BIT_H);
581 val &= ~(1 << MODE_BIT_L);
582 i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
583
584 i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
585 val |= (1 << MODE_BIT_H);
586 val &= ~(1 << MODE_BIT_L);
587 i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
588
589 }
590
board_late_init(void)591 int board_late_init(void)
592 {
593 #ifdef CONFIG_CMD_BMODE
594 add_board_boot_modes(board_boot_modes);
595 #endif
596
597 #if defined(CONFIG_VIDEO_IPUV3)
598 /*
599 * We need at least 200ms between power on and backlight on
600 * as per specifications from CHI MEI
601 */
602 mdelay(250);
603
604 /* enable backlight PWM 1 */
605 pwm_init(0, 0, 0);
606
607 /* duty cycle 5000000ns, period: 5000000ns */
608 pwm_config(0, 5000000, 5000000);
609
610 /* Backlight Power */
611 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
612
613 pwm_enable(0);
614 #endif
615
616 #ifdef CONFIG_SATA
617 setup_ba16_sata();
618 #endif
619
620 /* board specific pmic init */
621 pmic_init();
622
623 return 0;
624 }
625
checkboard(void)626 int checkboard(void)
627 {
628 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
629 return 0;
630 }
631