1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Allied Telesis Labs
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <dm.h>
9 #include <env.h>
10 #include <i2c.h>
11 #include <init.h>
12 #include <wdt.h>
13 #include <asm/global_data.h>
14 #include <asm/gpio.h>
15 #include <linux/bitops.h>
16 #include <linux/mbus.h>
17 #include <linux/io.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include "../common/gpio_hog.h"
21
22 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
23 #include <../serdes/a38x/high_speed_env_spec.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
28
29 #define CONFIG_NVS_LOCATION 0xf4800000
30 #define CONFIG_NVS_SIZE (512 << 10)
31
32 static struct serdes_map board_serdes_map[] = {
33 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
34 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
35 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
36 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
37 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
38 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
39 };
40
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)41 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
42 {
43 *serdes_map_array = board_serdes_map;
44 *count = ARRAY_SIZE(board_serdes_map);
45 return 0;
46 }
47
48 /*
49 * Define the DDR layout / topology here in the board file. This will
50 * be used by the DDR3 init code in the SPL U-Boot version to configure
51 * the DDR3 controller.
52 */
53 static struct mv_ddr_topology_map board_topology_map = {
54 DEBUG_LEVEL_ERROR,
55 0x1, /* active interfaces */
56 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
57 { { { {0x1, 0, 0, 0},
58 {0x1, 0, 0, 0},
59 {0x1, 0, 0, 0},
60 {0x1, 0, 0, 0},
61 {0x1, 0, 0, 0} },
62 SPEED_BIN_DDR_1866M, /* speed_bin */
63 MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
64 MV_DDR_DIE_CAP_4GBIT, /* die capacity */
65 MV_DDR_FREQ_SAR, /* frequency */
66 0, 0, /* cas_l cas_wl */
67 MV_DDR_TEMP_LOW, /* temperature */
68 MV_DDR_TIM_2T} }, /* timing */
69 BUS_MASK_32BIT_ECC, /* subphys mask */
70 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
71 NOT_COMBINED, /* ddr twin-die combined */
72 { {0} }, /* raw spd data */
73 {0}, /* timing parameters */
74 { {0} }, /* electrical configuration */
75 {0}, /* electrical parameters */
76 0, /* Clock enable mask */
77 160 /* Clock delay */
78 };
79
mv_ddr_topology_map_get(void)80 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
81 {
82 /* Return the board topology as defined in the board code */
83 return &board_topology_map;
84 }
85
board_early_init_f(void)86 int board_early_init_f(void)
87 {
88 /* Configure MPP */
89 writel(0x00001111, MVEBU_MPP_BASE + 0x00);
90 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
91 writel(0x55000000, MVEBU_MPP_BASE + 0x08);
92 writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
93 writel(0x55555555, MVEBU_MPP_BASE + 0x10);
94 writel(0x00100565, MVEBU_MPP_BASE + 0x14);
95 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
96 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
97
98 return 0;
99 }
100
spl_board_init(void)101 void spl_board_init(void)
102 {
103 }
104
board_init(void)105 int board_init(void)
106 {
107 /* address of boot parameters */
108 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
109
110 /* window for NVS */
111 mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
112 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
113
114 /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
115 writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
116
117 spl_board_init();
118
119 return 0;
120 }
121
arch_preboot_os(void)122 void arch_preboot_os(void)
123 {
124 #ifdef CONFIG_WATCHDOG
125 wdt_stop(gd->watchdog_dev);
126 #endif
127 }
128
led_7seg_init(unsigned int segments)129 static int led_7seg_init(unsigned int segments)
130 {
131 int node;
132 int ret;
133 int i;
134 struct gpio_desc desc[8];
135
136 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
137 "atl,of-led-7seg");
138 if (node < 0)
139 return -ENODEV;
140
141 ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
142 "segment-gpios", desc,
143 ARRAY_SIZE(desc), GPIOD_IS_OUT);
144 if (ret < 0)
145 return ret;
146
147 for (i = 0; i < ARRAY_SIZE(desc); i++) {
148 ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
149 if (ret)
150 return ret;
151 }
152
153 return 0;
154 }
155
156 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)157 int misc_init_r(void)
158 {
159 static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
160 led_en = {};
161
162 gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
163 gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
164 gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
165 gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
166
167 #ifdef MTDPARTS_MTDOOPS
168 env_set("mtdoops", MTDPARTS_MTDOOPS);
169 #endif
170
171 led_7seg_init(0xff);
172
173 return 0;
174 }
175 #endif
176
177 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)178 int checkboard(void)
179 {
180 puts("Board: " CONFIG_SYS_BOARD "\n");
181
182 return 0;
183 }
184 #endif
185