1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2020 Arm Limited
4 * Usama Arif <usama.arif@arm.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/platform_data/serial_pl01x.h>
10 #include <asm/armv8/mmu.h>
11 #include <asm/global_data.h>
12
13 static const struct pl01x_serial_plat serial_plat = {
14 .base = UART0_BASE,
15 .type = TYPE_PL011,
16 .clock = CONFIG_PL011_CLOCK,
17 };
18
19 U_BOOT_DRVINFO(total_compute_serials) = {
20 .name = "serial_pl01x",
21 .plat = &serial_plat,
22 };
23
24 static struct mm_region total_compute_mem_map[] = {
25 {
26 .virt = 0x0UL,
27 .phys = 0x0UL,
28 .size = 0x80000000UL,
29 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
30 PTE_BLOCK_NON_SHARE |
31 PTE_BLOCK_PXN | PTE_BLOCK_UXN
32 }, {
33 .virt = 0x80000000UL,
34 .phys = 0x80000000UL,
35 .size = 0xff80000000UL,
36 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
37 PTE_BLOCK_INNER_SHARE
38 }, {
39 /* List terminator */
40 0,
41 }
42 };
43
44 struct mm_region *mem_map = total_compute_mem_map;
45
board_init(void)46 int board_init(void)
47 {
48 return 0;
49 }
50
dram_init(void)51 int dram_init(void)
52 {
53 gd->ram_size = PHYS_SDRAM_1_SIZE;
54 return 0;
55 }
56
dram_init_banksize(void)57 int dram_init_banksize(void)
58 {
59 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
60 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
61
62 return 0;
63 }
64
65 /* Nothing to be done here as handled by PSCI interface */
reset_cpu(ulong addr)66 void reset_cpu(ulong addr)
67 {
68 }
69