1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) ARM Ltd 2015
4 *
5 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <linux/bitops.h>
13 #include <pci_ids.h>
14 #include <linux/delay.h>
15 #include "pcie.h"
16
17 /* XpressRICH3 support */
18 #define XR3_CONFIG_BASE 0x7ff30000
19 #define XR3_RESET_BASE 0x7ff20000
20
21 #define XR3_PCI_ECAM_START 0x40000000
22 #define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */
23 #define XR3_PCI_IOSPACE_START 0x5f800000
24 #define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */
25 #define XR3_PCI_MEMSPACE_START 0x50000000
26 #define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */
27 #define XR3_PCI_MEMSPACE64_START 0x4000000000
28 #define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */
29
30 #define JUNO_V2M_MSI_START 0x2c1c0000
31 #define JUNO_V2M_MSI_SIZE 12 /* as power of 2 = 4096 */
32
33 #define XR3PCI_BASIC_STATUS 0x18
34 #define XR3PCI_BS_GEN_MASK (0xf << 8)
35 #define XR3PCI_BS_LINK_MASK 0xff
36
37 #define XR3PCI_VIRTCHAN_CREDITS 0x90
38 #define XR3PCI_BRIDGE_PCI_IDS 0x9c
39 #define XR3PCI_PEX_SPC2 0xd8
40
41 #define XR3PCI_ATR_PCIE_WIN0 0x600
42 #define XR3PCI_ATR_PCIE_WIN1 0x700
43 #define XR3PCI_ATR_AXI4_SLV0 0x800
44
45 #define XR3PCI_ATR_TABLE_SIZE 0x20
46 #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
47 #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
48 #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
49 #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
50 #define XR3PCI_ATR_TRSL_PARAM 0x10
51
52 /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
53 #define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004)
54 #define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */
55 #define XR3PCI_ATR_TRSLID_PCIE_CONF (0x000001)
56 #define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000)
57 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000)
58
59 #define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \
60 (PCI_SLOT(d) << 15) | \
61 (PCI_FUNC(d) << 12) | o)
62
63 #define JUNO_RESET_CTRL 0x1004
64 #define JUNO_RESET_CTRL_PHY BIT(0)
65 #define JUNO_RESET_CTRL_RC BIT(1)
66
67 #define JUNO_RESET_STATUS 0x1008
68 #define JUNO_RESET_STATUS_PLL BIT(0)
69 #define JUNO_RESET_STATUS_PHY BIT(1)
70 #define JUNO_RESET_STATUS_RC BIT(2)
71 #define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \
72 JUNO_RESET_STATUS_PHY | \
73 JUNO_RESET_STATUS_RC)
74
xr3pci_set_atr_entry(unsigned long base,unsigned long src_addr,unsigned long trsl_addr,int window_size,int trsl_param)75 static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
76 unsigned long trsl_addr, int window_size,
77 int trsl_param)
78 {
79 /* X3PCI_ATR_SRC_ADDR_LOW:
80 - bit 0: enable entry,
81 - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
82 - bits 7-11: reserved
83 - bits 12-31: start of source address
84 */
85 writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
86 base + XR3PCI_ATR_SRC_ADDR_LOW);
87 writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
88 writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
89 writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
90 writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
91
92 debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
93 src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
94 ((u64)1) << window_size, trsl_param);
95 }
96
xr3pci_setup_atr(void)97 static void xr3pci_setup_atr(void)
98 {
99 /* setup PCIe to CPU address translation tables */
100 unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
101
102 /* forward all writes from PCIe to GIC V2M (used for MSI) */
103 xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
104 JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
105
106 base += XR3PCI_ATR_TABLE_SIZE;
107
108 /* PCIe devices can write anywhere in memory */
109 xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
110 31 /* grant access to all RAM under 4GB */,
111 XR3PCI_ATR_TRSLID_AXIMEMORY);
112 base += XR3PCI_ATR_TABLE_SIZE;
113 xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
114 XR3_PCI_MEMSPACE64_SIZE,
115 XR3PCI_ATR_TRSLID_AXIMEMORY);
116
117
118 /* setup CPU to PCIe address translation table */
119 base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
120
121 /* setup ECAM space to bus configuration interface */
122 xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
123 XR3PCI_ATR_TRSLID_PCIE_CONF);
124
125 base += XR3PCI_ATR_TABLE_SIZE;
126
127 /* setup IO space translation */
128 xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
129 XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
130
131 base += XR3PCI_ATR_TABLE_SIZE;
132
133 /* setup 32bit MEM space translation */
134 xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
135 XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
136
137 base += XR3PCI_ATR_TABLE_SIZE;
138
139 /* setup 64bit MEM space translation */
140 xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
141 XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
142 }
143
xr3pci_init(void)144 static void xr3pci_init(void)
145 {
146 u32 val;
147 int timeout = 200;
148
149 /* Initialise the XpressRICH3 PCIe host bridge */
150
151 /* add credits */
152 writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
153 writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
154 /* allow ECRC */
155 writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
156 /* setup the correct class code for the host bridge */
157 writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
158
159 /* reset phy and root complex */
160 writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
161 XR3_RESET_BASE + JUNO_RESET_CTRL);
162
163 do {
164 mdelay(1);
165 val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
166 } while (--timeout &&
167 (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
168
169 if (!timeout) {
170 printf("PCI XR3 Root complex reset timed out\n");
171 return;
172 }
173
174 /* Wait for the link to train */
175 mdelay(20);
176 timeout = 20;
177
178 do {
179 mdelay(1);
180 val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
181 } while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
182
183 if (!(val & XR3PCI_BS_LINK_MASK)) {
184 printf("Failed to negotiate a link!\n");
185 return;
186 }
187
188 printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
189 val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
190
191 xr3pci_setup_atr();
192 }
193
vexpress64_pcie_init(void)194 void vexpress64_pcie_init(void)
195 {
196 /* Initialise and configure the PCIe host bridge. */
197 xr3pci_init();
198
199 /* Register the now ECAM complaint PCIe host controller with U-Boot. */
200 pci_init();
201 }
202