1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
6 */
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <errno.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <linux/compiler.h>
18 #include <dm/platform_data/serial_pl01x.h>
19 #include "pcie.h"
20 #include <asm/armv8/mmu.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 static const struct pl01x_serial_plat serial_plat = {
25 .base = V2M_UART0,
26 .type = TYPE_PL011,
27 .clock = CONFIG_PL011_CLOCK,
28 };
29
30 U_BOOT_DRVINFO(vexpress_serials) = {
31 .name = "serial_pl01x",
32 .plat = &serial_plat,
33 };
34
35 static struct mm_region vexpress64_mem_map[] = {
36 {
37 .virt = 0x0UL,
38 .phys = 0x0UL,
39 .size = 0x80000000UL,
40 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
41 PTE_BLOCK_NON_SHARE |
42 PTE_BLOCK_PXN | PTE_BLOCK_UXN
43 }, {
44 .virt = 0x80000000UL,
45 .phys = 0x80000000UL,
46 .size = 0xff80000000UL,
47 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
48 PTE_BLOCK_INNER_SHARE
49 }, {
50 /* List terminator */
51 0,
52 }
53 };
54
55 struct mm_region *mem_map = vexpress64_mem_map;
56
57 /* This function gets replaced by platforms supporting PCIe.
58 * The replacement function, eg. on Juno, initialises the PCIe bus.
59 */
vexpress64_pcie_init(void)60 __weak void vexpress64_pcie_init(void)
61 {
62 }
63
board_init(void)64 int board_init(void)
65 {
66 vexpress64_pcie_init();
67 return 0;
68 }
69
dram_init(void)70 int dram_init(void)
71 {
72 gd->ram_size = PHYS_SDRAM_1_SIZE;
73 return 0;
74 }
75
dram_init_banksize(void)76 int dram_init_banksize(void)
77 {
78 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
79 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
80 #ifdef PHYS_SDRAM_2
81 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
82 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
83 #endif
84
85 return 0;
86 }
87
88 #ifdef CONFIG_OF_BOARD
89 #define JUNO_FLASH_SEC_SIZE (256 * 1024)
find_dtb_in_nor_flash(const char * partname)90 static phys_addr_t find_dtb_in_nor_flash(const char *partname)
91 {
92 phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
93 int i;
94
95 for (i = 0;
96 i < CONFIG_SYS_MAX_FLASH_SECT;
97 i++, sector += JUNO_FLASH_SEC_SIZE) {
98 int len = strlen(partname) + 1;
99 int offs;
100 phys_addr_t imginfo;
101 u32 reg;
102
103 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
104 /* This makes up the string "HSLFTOOF" flash footer */
105 if (reg != 0x464F4F54U)
106 continue;
107 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
108 if (reg != 0x464C5348U)
109 continue;
110
111 for (offs = 0; offs < 32; offs += 4, len -= 4) {
112 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
113 if (strncmp(partname + offs, (char *)®,
114 len > 4 ? 4 : len))
115 break;
116
117 if (len > 4)
118 continue;
119
120 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
121 imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
122 reg = readl(imginfo + 0x54);
123
124 return CONFIG_SYS_FLASH_BASE +
125 reg * JUNO_FLASH_SEC_SIZE;
126 }
127 }
128
129 printf("No DTB found\n");
130
131 return ~0;
132 }
133
board_fdt_blob_setup(void)134 void *board_fdt_blob_setup(void)
135 {
136 phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
137
138 if (fdt_rom_addr == ~0UL)
139 return NULL;
140
141 return (void *)fdt_rom_addr;
142 }
143 #endif
144
145 /* Actual reset is done via PSCI. */
reset_cpu(ulong addr)146 void reset_cpu(ulong addr)
147 {
148 }
149
150 /*
151 * Board specific ethernet initialization routine.
152 */
board_eth_init(struct bd_info * bis)153 int board_eth_init(struct bd_info *bis)
154 {
155 int rc = 0;
156 #ifndef CONFIG_DM_ETH
157 #ifdef CONFIG_SMC91111
158 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
159 #endif
160 #ifdef CONFIG_SMC911X
161 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
162 #endif
163 #endif
164 return rc;
165 }
166