1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <serial.h>
11 #include <watchdog.h>
12 #include <command.h>
13 #include <asm/global_data.h>
14 #include <asm/m5329.h>
15 #include <asm/immap_5329.h>
16 #include <asm/io.h>
17 #include <linux/delay.h>
18
19 /* needed for astro bus: */
20 #include <asm/uart.h>
21 #include "astro.h"
22
23 DECLARE_GLOBAL_DATA_PTR;
24 extern void uart_port_conf(void);
25
checkboard(void)26 int checkboard(void)
27 {
28 puts("Board: ");
29 puts("ASTRO MCF5373L (Urmel) Board\n");
30 return 0;
31 }
32
dram_init(void)33 int dram_init(void)
34 {
35 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
36 sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
37
38 /*
39 * GPIO configuration for bus should be set correctly from reset,
40 * so we do not care! First, set up address space: at this point,
41 * we should be running from internal SRAM;
42 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
43 * and do not care where it is
44 */
45 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
46 &sdp->cs0);
47 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
48 &sdp->cs1);
49 /*
50 * I am not sure from the data sheet, but it seems burst length
51 * has to be 8 for the 16 bit data bus we use;
52 * so these values are for BL = 8
53 */
54 __raw_writel(0x33211530, &sdp->cfg1);
55 __raw_writel(0x56570000, &sdp->cfg2);
56 /* send PrechargeALL, REF and IREF remain cleared! */
57 __raw_writel(0xE1462C02, &sdp->ctrl);
58 udelay(1);
59 /* refresh SDRAM twice */
60 __raw_writel(0xE1462C04, &sdp->ctrl);
61 udelay(1);
62 __raw_writel(0xE1462C04, &sdp->ctrl);
63 /* init MR */
64 __raw_writel(0x008D0000, &sdp->mode);
65 /* initialize EMR */
66 __raw_writel(0x80010000, &sdp->mode);
67 /* wait until DLL is locked */
68 udelay(1);
69 /*
70 * enable automatic refresh, lock mode register,
71 * clear iref and ipall
72 */
73 __raw_writel(0x71462C00, &sdp->ctrl);
74 /* Dummy write to start SDRAM */
75 writel(0, CONFIG_SYS_SDRAM_BASE);
76 #endif
77
78 /*
79 * for get_ram_size() to work, both CS areas have to be
80 * configured, i.e. CS1 has to be explicitely disabled, else
81 * probing for memory will cause the SDRAM bus to hang!
82 * (Do not rely on the SDCS register(s) being set to 0x00000000
83 * during reset as stated in the data sheet.)
84 */
85 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
86 0x80000000 - CONFIG_SYS_SDRAM_BASE);
87
88 return 0;
89 }
90
91 #define UART_BASE MMAP_UART0
rs_serial_init(int port,int baud)92 int rs_serial_init(int port, int baud)
93 {
94 uart_t *uart;
95 u32 counter;
96
97 switch (port) {
98 case 0:
99 uart = (uart_t *)(MMAP_UART0);
100 break;
101 case 1:
102 uart = (uart_t *)(MMAP_UART1);
103 break;
104 case 2:
105 uart = (uart_t *)(MMAP_UART2);
106 break;
107 default:
108 uart = (uart_t *)(MMAP_UART0);
109 }
110
111 uart_port_conf();
112
113 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
114 writeb(UART_UCR_RESET_RX, &uart->ucr);
115 writeb(UART_UCR_RESET_TX, &uart->ucr);
116 writeb(UART_UCR_RESET_ERROR, &uart->ucr);
117 writeb(UART_UCR_RESET_MR, &uart->ucr);
118 __asm__ ("nop");
119
120 writeb(0, &uart->uimr);
121
122 /* write to CSR: RX/TX baud rate from timers */
123 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
124
125 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
126 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
127
128 /* Setting up BaudRate */
129 counter = (u32) (gd->bus_clk / (baud));
130 counter >>= 5;
131
132 /* write to CTUR: divide counter upper byte */
133 writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
134 /* write to CTLR: divide counter lower byte */
135 writeb((u8) (counter & 0x00ff), &uart->ubg2);
136
137 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
138
139 return 0;
140 }
141
astro_put_char(char ch)142 void astro_put_char(char ch)
143 {
144 uart_t *uart;
145 unsigned long timer;
146
147 uart = (uart_t *)(MMAP_UART0);
148 /*
149 * Wait for last character to go. Timeout of 6ms should
150 * be enough for our lowest baud rate of 2400.
151 */
152 timer = get_timer(0);
153 while (get_timer(timer) < 6) {
154 if (readb(&uart->usr) & UART_USR_TXRDY)
155 break;
156 }
157 writeb(ch, &uart->utb);
158
159 return;
160 }
161
astro_is_char(void)162 int astro_is_char(void)
163 {
164 uart_t *uart;
165
166 uart = (uart_t *)(MMAP_UART0);
167 return readb(&uart->usr) & UART_USR_RXRDY;
168 }
169
astro_get_char(void)170 int astro_get_char(void)
171 {
172 uart_t *uart;
173
174 uart = (uart_t *)(MMAP_UART0);
175 while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
176 return readb(&uart->urb);
177 }
178
misc_init_r(void)179 int misc_init_r(void)
180 {
181 int retval = 0;
182
183 puts("Configure Xilinx FPGA...");
184 retval = astro5373l_xilinx_load();
185 if (!retval) {
186 puts("failed!\n");
187 return retval;
188 }
189 puts("done\n");
190
191 puts("Configure Altera FPGA...");
192 retval = astro5373l_altera_load();
193 if (!retval) {
194 puts("failed!\n");
195 return retval;
196 }
197 puts("done\n");
198
199 return retval;
200 }
201