1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <flash.h>
11 #include <init.h>
12 #include <net.h>
13 #include <vsprintf.h>
14 #include <asm/global_data.h>
15 #include <linux/sizes.h>
16 #include <asm/arch/at91sam9263.h>
17 #include <asm/arch/at91sam9_smc.h>
18 #include <asm/arch/at91_common.h>
19 #include <asm/arch/at91_matrix.h>
20 #include <asm/arch/at91_pio.h>
21 #include <asm/arch/clk.h>
22 #include <asm/io.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/hardware.h>
25 #include <lcd.h>
26 #include <atmel_lcdc.h>
27 #include <asm/mach-types.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /* ------------------------------------------------------------------------- */
32 /*
33 * Miscelaneous platform dependent initialisations
34 */
35
36 #ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init(void)37 static void at91sam9263ek_nand_hw_init(void)
38 {
39 unsigned long csa;
40 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
41 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
42
43 /* Enable CS3 */
44 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
45 writel(csa, &matrix->csa[0]);
46
47 /* Enable CS3 */
48
49 /* Configure SMC CS3 for NAND/SmartMedia */
50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
51 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
52 &smc->cs[3].setup);
53
54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
55 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
56 &smc->cs[3].pulse);
57
58 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
59 &smc->cs[3].cycle);
60 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
61 AT91_SMC_MODE_EXNW_DISABLE |
62 #ifdef CONFIG_SYS_NAND_DBW_16
63 AT91_SMC_MODE_DBW_16 |
64 #else /* CONFIG_SYS_NAND_DBW_8 */
65 AT91_SMC_MODE_DBW_8 |
66 #endif
67 AT91_SMC_MODE_TDF_CYCLE(2),
68 &smc->cs[3].mode);
69
70 at91_periph_clk_enable(ATMEL_ID_PIOA);
71 at91_periph_clk_enable(ATMEL_ID_PIOCDE);
72
73 /* Configure RDY/BSY */
74 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
75
76 /* Enable NandFlash */
77 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
78 }
79 #endif
80
81 #ifdef CONFIG_LCD
82 vidinfo_t panel_info = {
83 .vl_col = 240,
84 .vl_row = 320,
85 .vl_clk = 4965000,
86 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
87 ATMEL_LCDC_INVFRAME_INVERTED,
88 .vl_bpix = 3,
89 .vl_tft = 1,
90 .vl_hsync_len = 5,
91 .vl_left_margin = 1,
92 .vl_right_margin = 33,
93 .vl_vsync_len = 1,
94 .vl_upper_margin = 1,
95 .vl_lower_margin = 0,
96 .mmio = ATMEL_BASE_LCDC,
97 };
98
lcd_enable(void)99 void lcd_enable(void)
100 {
101 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
102 }
103
lcd_disable(void)104 void lcd_disable(void)
105 {
106 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
107 }
108
at91sam9263ek_lcd_hw_init(void)109 static void at91sam9263ek_lcd_hw_init(void)
110 {
111 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
112 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
113 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
114 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
115 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
116 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
117 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
118 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
119 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
120 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
121 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
122 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
123 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
124 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
125 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
126 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
127 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
128 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
129 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
130 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
131 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
132 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
133
134 at91_periph_clk_enable(ATMEL_ID_LCDC);
135 gd->fb_base = ATMEL_BASE_SRAM0;
136 }
137
138 #ifdef CONFIG_LCD_INFO
139 #include <nand.h>
140 #include <version.h>
141
142 #ifdef CONFIG_MTD_NOR_FLASH
143 extern flash_info_t flash_info[];
144 #endif
145
lcd_show_board_info(void)146 void lcd_show_board_info(void)
147 {
148 ulong dram_size, nand_size;
149 #ifdef CONFIG_MTD_NOR_FLASH
150 ulong flash_size;
151 #endif
152 int i;
153 char temp[32];
154
155 lcd_printf ("%s\n", U_BOOT_VERSION);
156 lcd_printf ("(C) 2008 ATMEL Corp\n");
157 lcd_printf ("at91support@atmel.com\n");
158 lcd_printf ("%s CPU at %s MHz\n",
159 ATMEL_CPU_NAME,
160 strmhz(temp, get_cpu_clk_rate()));
161
162 dram_size = 0;
163 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
164 dram_size += gd->bd->bi_dram[i].size;
165 nand_size = 0;
166 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
167 nand_size += get_nand_dev_by_index(i)->size;
168 #ifdef CONFIG_MTD_NOR_FLASH
169 flash_size = 0;
170 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
171 flash_size += flash_info[i].size;
172 #endif
173 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
174 dram_size >> 20,
175 nand_size >> 20 );
176 #ifdef CONFIG_MTD_NOR_FLASH
177 lcd_printf (",\n %ld MB NOR",
178 flash_size >> 20);
179 #endif
180 lcd_puts ("\n");
181 }
182 #endif /* CONFIG_LCD_INFO */
183 #endif
184
185 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)186 void board_debug_uart_init(void)
187 {
188 at91_seriald_hw_init();
189 }
190 #endif
191
192 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)193 int board_early_init_f(void)
194 {
195 #ifdef CONFIG_DEBUG_UART
196 debug_uart_init();
197 #endif
198 return 0;
199 }
200 #endif
201
board_init(void)202 int board_init(void)
203 {
204 /* arch number of AT91SAM9263EK-Board */
205 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
206 /* adress of boot parameters */
207 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
208
209 #ifdef CONFIG_CMD_NAND
210 at91sam9263ek_nand_hw_init();
211 #endif
212 #ifdef CONFIG_USB_OHCI_NEW
213 at91_uhp_hw_init();
214 #endif
215 #ifdef CONFIG_LCD
216 at91sam9263ek_lcd_hw_init();
217 #endif
218 return 0;
219 }
220
dram_init(void)221 int dram_init(void)
222 {
223 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
224 CONFIG_SYS_SDRAM_SIZE);
225
226 return 0;
227 }
228
229 #ifdef CONFIG_RESET_PHY_R
reset_phy(void)230 void reset_phy(void)
231 {
232 }
233 #endif
234