1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
4 *
5 * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
6 */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <init.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/at91_common.h>
14 #include <asm/arch/atmel_pio4.h>
15 #include <asm/arch/atmel_mpddrc.h>
16 #include <asm/arch/atmel_sdhci.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/sama5d2.h>
20
21 extern void at91_pda_detect(void);
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)26 int board_late_init(void)
27 {
28 #ifdef CONFIG_DM_VIDEO
29 at91_video_show_board_info();
30 #endif
31 at91_pda_detect();
32 return 0;
33 }
34 #endif
35
36 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_uart0_hw_init(void)37 static void board_uart0_hw_init(void)
38 {
39 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
40 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
41
42 at91_periph_clk_enable(ATMEL_ID_UART0);
43 }
44
board_debug_uart_init(void)45 void board_debug_uart_init(void)
46 {
47 board_uart0_hw_init();
48 }
49 #endif
50
51 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)52 int board_early_init_f(void)
53 {
54 #ifdef CONFIG_DEBUG_UART
55 debug_uart_init();
56 #endif
57
58 return 0;
59 }
60 #endif
61
board_init(void)62 int board_init(void)
63 {
64 /* address of boot parameters */
65 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
66
67 return 0;
68 }
69
70 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)71 int misc_init_r(void)
72 {
73 #ifdef CONFIG_SPI_FLASH_SFDP_SUPPORT
74 at91_spi_nor_set_ethaddr();
75 #endif
76 return 0;
77 }
78 #endif
79
dram_init(void)80 int dram_init(void)
81 {
82 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
83 CONFIG_SYS_SDRAM_SIZE);
84 return 0;
85 }
86
87 /* SPL */
88 #ifdef CONFIG_SPL_BUILD
89
board_leds_init(void)90 static void board_leds_init(void)
91 {
92 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* RED */
93 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 1); /* GREEN */
94 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 0); /* BLUE */
95 }
96
97 #ifdef CONFIG_SD_BOOT
spl_mmc_init(void)98 void spl_mmc_init(void)
99 {
100 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
101 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
102 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
103 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
104 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
105 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
106 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
107
108 at91_periph_clk_enable(ATMEL_ID_SDMMC0);
109 }
110 #endif
111
112 #ifdef CONFIG_QSPI_BOOT
spl_qspi_init(void)113 void spl_qspi_init(void)
114 {
115 atmel_pio4_set_d_periph(AT91_PIO_PORTB, 5, 0); /* SCK */
116 atmel_pio4_set_d_periph(AT91_PIO_PORTB, 6, 0); /* CS */
117 atmel_pio4_set_d_periph(AT91_PIO_PORTB, 7, 0); /* IO0 */
118 atmel_pio4_set_d_periph(AT91_PIO_PORTB, 8, 0); /* IO1 */
119 atmel_pio4_set_d_periph(AT91_PIO_PORTB, 9, 0); /* IO2 */
120 atmel_pio4_set_d_periph(AT91_PIO_PORTB, 10, 0); /* IO3 */
121
122 at91_periph_clk_enable(ATMEL_ID_QSPI1);
123 }
124 #endif
125
spl_board_init(void)126 void spl_board_init(void)
127 {
128 board_leds_init();
129 #ifdef CONFIG_SD_BOOT
130 spl_mmc_init();
131 #endif
132 #ifdef CONFIG_QSPI_BOOT
133 spl_qspi_init();
134 #endif
135 }
136
spl_display_print(void)137 void spl_display_print(void)
138 {
139 }
140
ddrc_conf(struct atmel_mpddrc_config * ddrc)141 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
142 {
143 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
144
145 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
146 ATMEL_MPDDRC_CR_NR_ROW_14 |
147 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
148 ATMEL_MPDDRC_CR_ZQ_SHORT |
149 ATMEL_MPDDRC_CR_NB_8BANKS |
150 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
151 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
152
153 ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
154
155 /*
156 * The AD220032D average time between REFRESH commands (Trefi): 3.9us
157 * 3.9us * 164MHz = 639.6 = 0x27F.
158 */
159 ddrc->rtr = 0x27f;
160 /* Enable Adjust Refresh Rate */
161 ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
162
163 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
164 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
165 (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
166 (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
167 (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
168 (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
169 (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
170 (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
171
172 ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
173 (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
174 (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
175 (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
176
177 ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
178 (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
179 (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
180 (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
181 (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
182
183 ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15);
184
185 /*
186 * According to the sama5d2 datasheet and the following values:
187 * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
188 * Warning: note that the values T driftrate and V driftrate are dependent on
189 * the application environment.
190 * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
191 * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize
192 * this timer to 0xFFFE.
193 */
194 ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE);
195
196 /*
197 * MR4 Read interval is dependent on the application environment.
198 * Here, we want to maximize this value as temperature is supposed
199 * to vary slowly in the application chosen.
200 * If Trefi is 3.9us, we have:
201 * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads.
202 */
203 ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
204 }
205
mem_init(void)206 void mem_init(void)
207 {
208 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
209 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
210 struct atmel_mpddrc_config ddrc_config;
211 u32 reg;
212
213 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
214 writel(AT91_PMC_DDR, &pmc->scer);
215
216 ddrc_conf(&ddrc_config);
217
218 reg = readl(&mpddrc->io_calibr);
219 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
220 reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48;
221 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
222 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
223 writel(reg, &mpddrc->io_calibr);
224
225 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
226 &mpddrc->rd_data_path);
227
228 lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
229 }
230
at91_pmc_init(void)231 void at91_pmc_init(void)
232 {
233 u32 tmp;
234
235 /*
236 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
237 * so we need to slow down and configure MCKR accordingly.
238 * This is why we have a special flavor of the switching function.
239 */
240 tmp = AT91_PMC_MCKR_PLLADIV_2 |
241 AT91_PMC_MCKR_MDIV_3 |
242 AT91_PMC_MCKR_CSS_MAIN;
243 at91_mck_init_down(tmp);
244
245 tmp = AT91_PMC_PLLAR_29 |
246 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
247 AT91_PMC_PLLXR_MUL(40) |
248 AT91_PMC_PLLXR_DIV(1);
249 at91_plla_init(tmp);
250
251 tmp = AT91_PMC_MCKR_H32MXDIV |
252 AT91_PMC_MCKR_PLLADIV_2 |
253 AT91_PMC_MCKR_MDIV_3 |
254 AT91_PMC_MCKR_CSS_PLLA;
255 at91_mck_init(tmp);
256 }
257 #endif
258