1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
5 */
6
7 #include <common.h>
8 #include <debug_uart.h>
9 #include <init.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/atmel_pio4.h>
14 #include <asm/arch/atmel_mpddrc.h>
15 #include <asm/arch/atmel_sdhci.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/sama5d2.h>
19
20 extern void at91_pda_detect(void);
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 #ifdef CONFIG_CMD_USB
board_usb_hw_init(void)25 static void board_usb_hw_init(void)
26 {
27 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
28 }
29 #endif
30
31 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)32 int board_late_init(void)
33 {
34 #ifdef CONFIG_DM_VIDEO
35 at91_video_show_board_info();
36 #endif
37 at91_pda_detect();
38 return 0;
39 }
40 #endif
41
42 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_uart1_hw_init(void)43 static void board_uart1_hw_init(void)
44 {
45 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */
46 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
47
48 at91_periph_clk_enable(ATMEL_ID_UART1);
49 }
50
board_debug_uart_init(void)51 void board_debug_uart_init(void)
52 {
53 board_uart1_hw_init();
54 }
55 #endif
56
57 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)58 int board_early_init_f(void)
59 {
60 #ifdef CONFIG_DEBUG_UART
61 debug_uart_init();
62 #endif
63
64 return 0;
65 }
66 #endif
67
board_init(void)68 int board_init(void)
69 {
70 /* address of boot parameters */
71 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
72
73 #ifdef CONFIG_CMD_USB
74 board_usb_hw_init();
75 #endif
76
77 return 0;
78 }
79
dram_init(void)80 int dram_init(void)
81 {
82 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
83 CONFIG_SYS_SDRAM_SIZE);
84 return 0;
85 }
86
87 #define AT24MAC_MAC_OFFSET 0x9a
88
89 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)90 int misc_init_r(void)
91 {
92 #ifdef CONFIG_I2C_EEPROM
93 at91_set_ethaddr(AT24MAC_MAC_OFFSET);
94 #endif
95
96 return 0;
97 }
98 #endif
99
100 /* SPL */
101 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)102 void spl_board_init(void)
103 {
104 }
105
ddrc_conf(struct atmel_mpddrc_config * ddrc)106 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
107 {
108 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
109
110 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
111 ATMEL_MPDDRC_CR_NR_ROW_14 |
112 ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
113 ATMEL_MPDDRC_CR_DIC_DS |
114 ATMEL_MPDDRC_CR_DIS_DLL |
115 ATMEL_MPDDRC_CR_NB_8BANKS |
116 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
117 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
118
119 ddrc->rtr = 0x511;
120
121 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
122 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
123 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
124 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
125 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
126 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
127 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
128 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
129
130 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
131 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
132 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
133 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
134
135 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
136 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
137 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
138 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
139 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
140 }
141
mem_init(void)142 void mem_init(void)
143 {
144 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
145 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
146 struct atmel_mpddrc_config ddrc_config;
147 u32 reg;
148
149 ddrc_conf(&ddrc_config);
150
151 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
152 writel(AT91_PMC_DDR, &pmc->scer);
153
154 reg = readl(&mpddrc->io_calibr);
155 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
156 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
157 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
158 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
159 writel(reg, &mpddrc->io_calibr);
160
161 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
162 &mpddrc->rd_data_path);
163
164 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
165
166 writel(0x3, &mpddrc->cal_mr4);
167 writel(64, &mpddrc->tim_cal);
168 }
169
at91_pmc_init(void)170 void at91_pmc_init(void)
171 {
172 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
173 u32 tmp;
174
175 /*
176 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
177 * so we need to slow down and configure MCKR accordingly.
178 * This is why we have a special flavor of the switching function.
179 */
180 tmp = AT91_PMC_MCKR_PLLADIV_2 |
181 AT91_PMC_MCKR_MDIV_3 |
182 AT91_PMC_MCKR_CSS_MAIN;
183 at91_mck_init_down(tmp);
184
185 tmp = AT91_PMC_PLLAR_29 |
186 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
187 AT91_PMC_PLLXR_MUL(82) |
188 AT91_PMC_PLLXR_DIV(1);
189 at91_plla_init(tmp);
190
191 writel(0x0 << 8, &pmc->pllicpr);
192
193 tmp = AT91_PMC_MCKR_H32MXDIV |
194 AT91_PMC_MCKR_PLLADIV_2 |
195 AT91_PMC_MCKR_MDIV_3 |
196 AT91_PMC_MCKR_CSS_PLLA;
197 at91_mck_init(tmp);
198 }
199 #endif
200