1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014, Bachmann electronic GmbH
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <net.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <env.h>
16 #include <malloc.h>
17 #include <asm/arch/mx6-pins.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/sata.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/sys_proto.h>
24 #include <mmc.h>
25 #include <fsl_esdhc_imx.h>
26 #include <netdev.h>
27 #include <i2c.h>
28 #include <pca953x.h>
29 #include <asm/gpio.h>
30 #include <phy.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
35
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
44 PAD_CTL_HYS)
45
46 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
47 PAD_CTL_SRE_FAST)
48
49 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
50 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
dram_init(void)52 int dram_init(void)
53 {
54 gd->ram_size = imx_ddr_size();
55
56 return 0;
57 }
58
59 static iomux_v3_cfg_t const uart1_pads[] = {
60 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
61 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
62 };
63
setup_iomux_uart(void)64 static void setup_iomux_uart(void)
65 {
66 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
67 }
68
69 static iomux_v3_cfg_t const enet_pads[] = {
70 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 };
88
setup_iomux_enet(void)89 static void setup_iomux_enet(void)
90 {
91 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
92 }
93
94 static iomux_v3_cfg_t const ecspi1_pads[] = {
95 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
96 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
97 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
98 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
99 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
100 };
101
setup_iomux_spi(void)102 static void setup_iomux_spi(void)
103 {
104 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
105 }
106
board_spi_cs_gpio(unsigned bus,unsigned cs)107 int board_spi_cs_gpio(unsigned bus, unsigned cs)
108 {
109 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
110 }
111
112 static iomux_v3_cfg_t const feature_pads[] = {
113 /* SD card detect */
114 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
115
116 /* eMMC soldered? */
117 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
118 };
119
setup_iomux_features(void)120 static void setup_iomux_features(void)
121 {
122 imx_iomux_v3_setup_multiple_pads(feature_pads,
123 ARRAY_SIZE(feature_pads));
124 }
125
126 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
127
128 /* I2C2 - EEPROM */
129 static struct i2c_pads_info i2c_pad_info1 = {
130 .scl = {
131 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
132 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
133 .gp = IMX_GPIO_NR(2, 30)
134 },
135 .sda = {
136 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
137 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
138 .gp = IMX_GPIO_NR(3, 16)
139 }
140 };
141
142 /* I2C3 - IO expander */
143 static struct i2c_pads_info i2c_pad_info2 = {
144 .scl = {
145 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
146 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
147 .gp = IMX_GPIO_NR(3, 17)
148 },
149 .sda = {
150 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
151 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
152 .gp = IMX_GPIO_NR(3, 18)
153 }
154 };
155
setup_iomux_i2c(void)156 static void setup_iomux_i2c(void)
157 {
158 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
159 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
160 }
161
ccgr_init(void)162 static void ccgr_init(void)
163 {
164 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
165
166 writel(0x00C03F3F, &ccm->CCGR0);
167 writel(0x0030FC33, &ccm->CCGR1);
168 writel(0x0FFFC000, &ccm->CCGR2);
169 writel(0x3FF00000, &ccm->CCGR3);
170 writel(0x00FFF300, &ccm->CCGR4);
171 writel(0x0F0000C3, &ccm->CCGR5);
172 writel(0x000003FF, &ccm->CCGR6);
173 }
174
board_early_init_f(void)175 int board_early_init_f(void)
176 {
177 ccgr_init();
178 gpr_init();
179
180 setup_iomux_uart();
181 setup_iomux_spi();
182 setup_iomux_i2c();
183 setup_iomux_features();
184
185 return 0;
186 }
187
188 static iomux_v3_cfg_t const usdhc3_pads[] = {
189 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
190 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
191 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
192 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
193 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
194 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
195 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
196 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
197 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
198 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
199 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
200 };
201
202 iomux_v3_cfg_t const usdhc4_pads[] = {
203 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
204 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
205 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
206 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
207 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
208 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
209 };
210
board_mmc_getcd(struct mmc * mmc)211 int board_mmc_getcd(struct mmc *mmc)
212 {
213 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
214 int ret;
215
216 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
217 gpio_direction_input(IMX_GPIO_NR(4, 5));
218 ret = gpio_get_value(IMX_GPIO_NR(4, 5));
219 } else {
220 gpio_direction_input(IMX_GPIO_NR(1, 5));
221 ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
222 }
223
224 return ret;
225 }
226
227 struct fsl_esdhc_cfg usdhc_cfg[2] = {
228 {USDHC3_BASE_ADDR},
229 {USDHC4_BASE_ADDR},
230 };
231
board_mmc_init(struct bd_info * bis)232 int board_mmc_init(struct bd_info *bis)
233 {
234 int ret;
235 u32 index = 0;
236
237 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
238 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
239
240 usdhc_cfg[0].max_bus_width = 8;
241 usdhc_cfg[1].max_bus_width = 4;
242
243 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
244 switch (index) {
245 case 0:
246 imx_iomux_v3_setup_multiple_pads(
247 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
248 break;
249 case 1:
250 imx_iomux_v3_setup_multiple_pads(
251 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
252 break;
253 default:
254 printf("Warning: you configured more USDHC controllers"
255 "(%d) then supported by the board (%d)\n",
256 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
257 return -EINVAL;
258 }
259
260 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
261 if (ret)
262 return ret;
263 }
264
265 return 0;
266 }
267
leds_on(void)268 static void leds_on(void)
269 {
270 /* turn on all possible leds connected via GPIO expander */
271 i2c_set_bus_num(2);
272 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
273 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
274 }
275
backlight_lcd_off(void)276 static void backlight_lcd_off(void)
277 {
278 unsigned gpio = IMX_GPIO_NR(2, 0);
279 gpio_direction_output(gpio, 0);
280
281 gpio = IMX_GPIO_NR(2, 3);
282 gpio_direction_output(gpio, 0);
283 }
284
board_eth_init(struct bd_info * bis)285 int board_eth_init(struct bd_info *bis)
286 {
287 uint32_t base = IMX_FEC_BASE;
288 struct mii_dev *bus = NULL;
289 struct phy_device *phydev = NULL;
290 int ret;
291
292 setup_iomux_enet();
293
294 bus = fec_get_miibus(base, -1);
295 if (!bus)
296 return -EINVAL;
297
298 /* scan phy 0 and 5 */
299 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
300 if (!phydev) {
301 ret = -EINVAL;
302 goto free_bus;
303 }
304
305 /* depending on the phy address we can detect our board version */
306 if (phydev->addr == 0)
307 env_set("boardver", "");
308 else
309 env_set("boardver", "mr");
310
311 printf("using phy at %d\n", phydev->addr);
312 ret = fec_probe(bis, -1, base, bus, phydev);
313 if (ret)
314 goto free_phydev;
315
316 return 0;
317
318 free_phydev:
319 free(phydev);
320 free_bus:
321 free(bus);
322 return ret;
323 }
324
board_init(void)325 int board_init(void)
326 {
327 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
328
329 backlight_lcd_off();
330
331 leds_on();
332
333 #ifdef CONFIG_SATA
334 setup_sata();
335 #endif
336
337 return 0;
338 }
339
checkboard(void)340 int checkboard(void)
341 {
342 puts("Board: "CONFIG_SYS_BOARD"\n");
343 return 0;
344 }
345
346 #ifdef CONFIG_CMD_BMODE
347 static const struct boot_mode board_boot_modes[] = {
348 /* 4 bit bus width */
349 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
350 {NULL, 0},
351 };
352 #endif
353
misc_init_r(void)354 int misc_init_r(void)
355 {
356 #ifdef CONFIG_CMD_BMODE
357 add_board_boot_modes(board_boot_modes);
358 #endif
359 return 0;
360 }
361