1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Barco (www.barco.com)
4 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <mmc.h>
10 #include <fsl_esdhc_imx.h>
11 #include <miiphy.h>
12 #include <net.h>
13 #include <netdev.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/gpio.h>
23 #include <asm/mach-imx/iomux-v3.h>
24 #include <asm/mach-imx/boot_mode.h>
25
26 #include "platinum.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 iomux_v3_cfg_t const usdhc3_pads[] = {
31 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
32 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
33 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
34 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
35 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
36 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
37 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
38 };
39
40 iomux_v3_cfg_t nfc_pads[] = {
41 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
42 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
43 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
44 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
45 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
46 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
47 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
48 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
49 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
50 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
51 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
52 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
53 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
54 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
55 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
56 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
57 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
58 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
59 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
60 };
61
62 struct fsl_esdhc_cfg usdhc_cfg[] = {
63 { USDHC3_BASE_ADDR },
64 };
65
setup_gpmi_nand(void)66 void setup_gpmi_nand(void)
67 {
68 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
69
70 /* config gpmi nand iomux */
71 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
72
73 /* config gpmi and bch clock to 100 MHz */
74 clrsetbits_le32(&mxc_ccm->cs2cdr,
75 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
76 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
77 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
78 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
79 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
80 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
81
82 /* enable gpmi and bch clock gating */
83 setbits_le32(&mxc_ccm->CCGR4,
84 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
86 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
87 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
88 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
89
90 /* enable apbh clock gating */
91 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
92 }
93
dram_init(void)94 int dram_init(void)
95 {
96 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
97
98 return 0;
99 }
100
board_ehci_hcd_init(int port)101 int board_ehci_hcd_init(int port)
102 {
103 return 0;
104 }
105
board_mmc_getcd(struct mmc * mmc)106 int board_mmc_getcd(struct mmc *mmc)
107 {
108 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
109
110 if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
111 unsigned sd3_cd = IMX_GPIO_NR(7, 0);
112 gpio_direction_input(sd3_cd);
113 return !gpio_get_value(sd3_cd);
114 }
115
116 return 0;
117 }
118
board_mmc_init(struct bd_info * bis)119 int board_mmc_init(struct bd_info *bis)
120 {
121 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
122 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
123
124 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
125 }
126
board_init_gpio(void)127 void board_init_gpio(void)
128 {
129 platinum_init_gpio();
130 }
131
board_init_gpmi_nand(void)132 void board_init_gpmi_nand(void)
133 {
134 setup_gpmi_nand();
135 }
136
board_init_i2c(void)137 void board_init_i2c(void)
138 {
139 platinum_setup_i2c();
140 }
141
board_init_spi(void)142 void board_init_spi(void)
143 {
144 platinum_setup_spi();
145 }
146
board_init_uart(void)147 void board_init_uart(void)
148 {
149 platinum_setup_uart();
150 }
151
board_init_usb(void)152 void board_init_usb(void)
153 {
154 platinum_init_usb();
155 }
156
board_init_finished(void)157 void board_init_finished(void)
158 {
159 platinum_init_finished();
160 }
161
board_phy_config(struct phy_device * phydev)162 int board_phy_config(struct phy_device *phydev)
163 {
164 return platinum_phy_config(phydev);
165 }
166
board_eth_init(struct bd_info * bis)167 int board_eth_init(struct bd_info *bis)
168 {
169 return cpu_eth_init(bis);
170 }
171
board_early_init_f(void)172 int board_early_init_f(void)
173 {
174 board_init_uart();
175
176 return 0;
177 }
178
board_init(void)179 int board_init(void)
180 {
181 /* address of boot parameters */
182 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
183
184 board_init_spi();
185
186 board_init_i2c();
187
188 board_init_gpmi_nand();
189
190 board_init_gpio();
191
192 board_init_usb();
193
194 board_init_finished();
195
196 return 0;
197 }
198
checkboard(void)199 int checkboard(void)
200 {
201 puts("Board: " CONFIG_PLATINUM_BOARD "\n");
202 return 0;
203 }
204
205 static const struct boot_mode board_boot_modes[] = {
206 /* NAND */
207 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
208 /* 4 bit bus width */
209 { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
210 { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
211 { NULL, 0 },
212 };
213
misc_init_r(void)214 int misc_init_r(void)
215 {
216 add_board_boot_modes(board_boot_modes);
217
218 return 0;
219 }
220