1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Projectiondesign AS 4 * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg 5 * 6 * Copyright (C) 2011 Freescale Semiconductor, Inc. 7 * Jason Liu <r64343@freescale.com> 8 * 9 * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure 10 * and create imximage boot image 11 * 12 * The syntax is taken as close as possible with the kwbimage 13 */ 14 15/* image version */ 16 17IMAGE_VERSION 2 18 19/* 20 * Boot Device : one of 21 * sd, nand 22 */ 23BOOT_FROM nand 24 25/* 26 * Device Configuration Data (DCD) 27 * 28 * Each entry must have the format: 29 * Addr-type Address Value 30 * 31 * where: 32 * Addr-type register length (1,2 or 4 bytes) 33 * Address absolute address of the register 34 * value value to be stored in the register 35 */ 36 37#define __ASSEMBLY__ 38#include <config.h> 39#include "asm/arch/mx6-ddr.h" 40#include "asm/arch/iomux.h" 41#include "asm/arch/crm_regs.h" 42 43DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 44DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 45DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 46DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 47DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 48DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 49DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 50DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 51 52DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 53DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 54DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 55DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 56DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 57DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 58DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 59DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 60 61DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 62DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 63DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 64DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 65 66DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 67DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 68DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 69 70DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 71 72DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 73DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 74 75DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 76DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 77DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 78DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 79DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 80DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 81DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 82DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 83DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 84 85/* (differential input) */ 86DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 87/* disable ddr pullups */ 88DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 89/* (differential input) */ 90DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 91/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 92DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 93/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 94DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 95 96/* Read data DQ Byte0-3 delay */ 97DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 98DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 99DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 100DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 101DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 102DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 103DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 104DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 105 106/* 107 * MDMISC mirroring interleaved (row/bank/col) 108 */ 109DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 110 111DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 112DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 113DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 114DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 115DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 116DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 117DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 118DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 119DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 120DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 121DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 122DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A 123DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 124DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B 125DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 126DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 127DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 128DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 129DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 130DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 131DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 132DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 133DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 134DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 135DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 136DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 137DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 138DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 139DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 140DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B 141DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 142DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 143DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 144DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 145DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 146DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 147DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 148DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 149DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 150DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 151DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 152 153/* set the default clock gate to save power */ 154DATA 4, CCM_CCGR0, 0x00C03F3F 155DATA 4, CCM_CCGR1, 0x0030FC03 156DATA 4, CCM_CCGR2, 0x0FFFC000 157DATA 4, CCM_CCGR3, 0x3FF00000 158DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ 159DATA 4, CCM_CCGR5, 0x0F0000C3 160DATA 4, CCM_CCGR6, 0x000003FF 161 162/* enable AXI cache for VDOA/VPU/IPU */ 163DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 164/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 165DATA 4, MX6_IOMUXC_GPR6, 0x007F007F 166DATA 4, MX6_IOMUXC_GPR7, 0x007F007F 167