1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6 #include <common.h>
7 #include <hang.h>
8 #include <image.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <errno.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/ddr.h>
16 #include <asm/arch/imx8mn_pins.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/gpio.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <fsl_esdhc_imx.h>
24 #include <mmc.h>
25 #include <linux/delay.h>
26 #include <power/pmic.h>
27 #include <power/bd71837.h>
28 #include <spl.h>
29
30 #include <dm/uclass.h>
31 #include <dm/device.h>
32 #include <dm/uclass-internal.h>
33 #include <dm/device-internal.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
spl_board_boot_device(enum boot_device boot_dev_spl)37 int spl_board_boot_device(enum boot_device boot_dev_spl)
38 {
39 return BOOT_DEVICE_BOOTROM;
40 }
41
spl_dram_init(void)42 void spl_dram_init(void)
43 {
44 ddr_init(&dram_timing);
45 }
46
spl_board_init(void)47 void spl_board_init(void)
48 {
49 struct udevice *dev;
50 int ret;
51
52 debug("Normal Boot\n");
53
54 ret = uclass_get_device_by_name(UCLASS_CLK,
55 "clock-controller@30380000",
56 &dev);
57 if (ret < 0)
58 puts("Failed to find clock node. Check device tree\n");
59 }
60
61 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)62 int board_fit_config_name_match(const char *name)
63 {
64 /* Just empty function now - can't decide what to choose */
65 debug("%s: %s\n", __func__, name);
66
67 return 0;
68 }
69 #endif
70
71 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
72 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
73 #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
74
75 static iomux_v3_cfg_t const pwm_pads[] = {
76 IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
77 };
78
79 static iomux_v3_cfg_t const uart_pads[] = {
80 IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
81 IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
82 };
83
84 static iomux_v3_cfg_t const wdog_pads[] = {
85 IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
86 };
87
board_early_init_f(void)88 int board_early_init_f(void)
89 {
90 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
91
92 /* Claiming pwm pins prevents LCD flicker during startup*/
93 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
94
95 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
96 set_wdog_reset(wdog);
97
98 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
99 init_uart_clk(1);
100
101 return 0;
102 }
103
board_init_f(ulong dummy)104 void board_init_f(ulong dummy)
105 {
106 int ret;
107
108 /* Clear the BSS. */
109 memset(__bss_start, 0, __bss_end - __bss_start);
110
111 arch_cpu_init();
112
113 board_early_init_f();
114
115 timer_init();
116
117 preloader_console_init();
118
119 ret = spl_init();
120 if (ret) {
121 debug("spl_init() failed: %d\n", ret);
122 hang();
123 }
124
125 /* DDR initialization */
126 spl_dram_init();
127
128 board_init_r(NULL, 0);
129 }
130