1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
4 *
5 * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
6 * and create imximage boot image
7 *
8 * The syntax is taken as close as possible with the kwbimage
9 */
10
11/* image version */
12
13IMAGE_VERSION 2
14
15/*
16 * Boot Device : one of
17 * sd, nand
18 */
19BOOT_FROM      sd
20
21/*
22 * Device Configuration Data (DCD)
23 *
24 * Each entry must have the format:
25 * Addr-type           Address        Value
26 *
27 * where:
28 *      Addr-type register length (1,2 or 4 bytes)
29 *      Address   absolute address of the register
30 *      value     value to be stored in the register
31 */
32
33#define __ASSEMBLY__
34#include <config.h>
35
36/* Enable all clocks */
37DATA 4 0x020c4068 0xffffffff
38DATA 4 0x020c406c 0xffffffff
39DATA 4 0x020c4070 0xffffffff
40DATA 4 0x020c4074 0xffffffff
41DATA 4 0x020c4078 0xffffffff
42DATA 4 0x020c407c 0xffffffff
43DATA 4 0x020c4080 0xffffffff
44DATA 4 0x020c4084 0xffffffff
45
46/* ddr io type */
47DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
48DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
49
50/* clock */
51DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
52
53/* control and address */
54DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
55DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
56DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
57DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
58DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
59				configured using Group Control Register:
60				IOMUXC_SW_PAD_CTL_GRP_CTLDS */
61DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
62DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
63DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
64
65/* data strobes */
66DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
67DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
68DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
69
70/* data */
71DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
72DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
73DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
74DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
75DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
76
77/*
78 * DDR Controller Registers
79 *
80 * Manufacturer:  IM
81 * Device Part Number:  IME1G16D3EEBG-15EI
82 * Clock Freq.:   400MHz
83 * Density per CS in Gb: 1
84 * Chip Selects used: 1
85 * Number of Banks: 8
86 * Row address:     13
87 * Column address:  10
88 * Data bus width 16
89 */
90DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
91				during MMDC set up */
92
93/*
94 * Calibration setup
95 */
96DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
97				periodic HW ZQ calibration. */
98
99/*
100 * For target board, may need to run write leveling calibration to fine tune
101 * these settings.
102 */
103DATA 4 0x021b080c 0x00000000
104
105/* Read DQS Gating calibration */
106DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
107
108/* Read calibration */
109DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
110
111/* Write calibration */
112DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
113
114/*
115 * read data bit delay: (3 is the reccommended default value, although out of
116 * reset value is 0)
117 */
118DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
119DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
120DATA 4 0x021b082c 0xF3333333
121DATA 4 0x021b0830 0xF3333333
122
123DATA 4 0x021b08c0 0x00921012
124
125/* Clock Fine Tuning */
126DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
127
128/* Complete calibration by forced measurement: */
129DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
130/*
131 * Calibration setup end
132 */
133
134/* MMDC init: */
135DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
136DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
137DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
138DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
139DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
140
141/*
142 * MDMISC: RALAT kept to the high level of 5.
143 * MDMISC: consider reducing RALAT if your 528MHz board design allow that.
144 * Lower RALAT benefits:
145 * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
146 *    to 3
147 * b. Small performence improvment
148 */
149DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
150
151DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
152				during MMDC set up */
153
154DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
155DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
156DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
157DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
158
159/* Mode register writes */
160DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
161DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
162DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
163DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
164DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
165				device on CS0 */
166
167DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
168DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
169DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
170DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
171				enter automatically to self-refresh while the
172				number of idle cycle reached. */
173DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
174				the configuration bit as initialization is
175				complete) */
176