1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Creative ZEN X-Fi3 board
4 *
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 *
7 * Hardware investigation done by:
8 *
9 * Amaury Pouly <amaury.pouly@gmail.com>
10 */
11
12 #include <common.h>
13 #include <errno.h>
14 #include <init.h>
15 #include <net.h>
16 #include <asm/global_data.h>
17 #include <asm/gpio.h>
18 #include <asm/io.h>
19 #include <asm/arch/iomux-mx23.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/sys_proto.h>
23 #include <linux/delay.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 /*
28 * Functions
29 */
board_early_init_f(void)30 int board_early_init_f(void)
31 {
32 /* IO0 clock at 480MHz */
33 mxs_set_ioclk(MXC_IOCLK0, 480000);
34
35 /* SSP0 clock at 96MHz */
36 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
37
38 return 0;
39 }
40
dram_init(void)41 int dram_init(void)
42 {
43 return mxs_dram_init();
44 }
45
46 #ifdef CONFIG_CMD_MMC
xfi3_mmc_cd(int id)47 static int xfi3_mmc_cd(int id)
48 {
49 switch (id) {
50 case 0:
51 /* The SSP_DETECT is inverted on this board. */
52 return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
53 case 1:
54 /* Phison bridge always present */
55 return 1;
56 default:
57 return 0;
58 }
59 }
60
board_mmc_init(struct bd_info * bis)61 int board_mmc_init(struct bd_info *bis)
62 {
63 int ret;
64
65 /* MicroSD slot */
66 gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
67 gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
68 ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
69 if (ret)
70 return ret;
71
72 /* Phison SD-NAND bridge */
73 ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
74
75 return ret;
76 }
77 #endif
78
79 #ifdef CONFIG_VIDEO_MXS
mxsfb_write_byte(uint32_t payload,const unsigned int data)80 static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
81 {
82 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
83 const unsigned int timeout = 0x10000;
84
85 if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
86 timeout))
87 return -ETIMEDOUT;
88
89 writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
90 (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
91 ®s->hw_lcdif_transfer_count);
92
93 writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
94 ®s->hw_lcdif_ctrl_clr);
95
96 if (data)
97 writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
98
99 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
100
101 if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
102 timeout))
103 return -ETIMEDOUT;
104
105 writel(payload, ®s->hw_lcdif_data);
106 return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
107 timeout);
108 }
109
mxsfb_write_register(uint32_t reg,uint32_t data)110 static void mxsfb_write_register(uint32_t reg, uint32_t data)
111 {
112 mxsfb_write_byte(reg, 0);
113 mxsfb_write_byte(data, 1);
114 }
115
116 static const struct {
117 uint8_t reg;
118 uint8_t delay;
119 uint16_t val;
120 } lcd_regs[] = {
121 { 0x01, 0, 0x001c },
122 { 0x02, 0, 0x0100 },
123 /* Writing 0x30 to reg. 0x03 flips the LCD */
124 { 0x03, 0, 0x1038 },
125 { 0x08, 0, 0x0808 },
126 /* This can contain 0x111 to rotate the LCD. */
127 { 0x0c, 0, 0x0000 },
128 { 0x0f, 0, 0x0c01 },
129 { 0x20, 0, 0x0000 },
130 { 0x21, 30, 0x0000 },
131 /* Wait 30 mS here */
132 { 0x10, 0, 0x0a00 },
133 { 0x11, 30, 0x1038 },
134 /* Wait 30 mS here */
135 { 0x12, 0, 0x1010 },
136 { 0x13, 0, 0x0050 },
137 { 0x14, 0, 0x4f58 },
138 { 0x30, 0, 0x0000 },
139 { 0x31, 0, 0x00db },
140 { 0x32, 0, 0x0000 },
141 { 0x33, 0, 0x0000 },
142 { 0x34, 0, 0x00db },
143 { 0x35, 0, 0x0000 },
144 { 0x36, 0, 0x00af },
145 { 0x37, 0, 0x0000 },
146 { 0x38, 0, 0x00db },
147 { 0x39, 0, 0x0000 },
148 { 0x50, 0, 0x0000 },
149 { 0x51, 0, 0x0705 },
150 { 0x52, 0, 0x0e0a },
151 { 0x53, 0, 0x0300 },
152 { 0x54, 0, 0x0a0e },
153 { 0x55, 0, 0x0507 },
154 { 0x56, 0, 0x0000 },
155 { 0x57, 0, 0x0003 },
156 { 0x58, 0, 0x090a },
157 { 0x59, 30, 0x0a09 },
158 /* Wait 30 mS here */
159 { 0x07, 30, 0x1017 },
160 /* Wait 40 mS here */
161 { 0x36, 0, 0x00af },
162 { 0x37, 0, 0x0000 },
163 { 0x38, 0, 0x00db },
164 { 0x39, 0, 0x0000 },
165 { 0x20, 0, 0x0000 },
166 { 0x21, 0, 0x0000 },
167 };
168
mxsfb_system_setup(void)169 void mxsfb_system_setup(void)
170 {
171 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
172 int i;
173
174 /* Switch the LCDIF into System-Mode */
175 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
176 LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
177
178 /* Restart the SmartLCD controller */
179 mdelay(50);
180 writel(1, ®s->hw_lcdif_ctrl1_set);
181 mdelay(50);
182 writel(1, ®s->hw_lcdif_ctrl1_clr);
183 mdelay(50);
184 writel(1, ®s->hw_lcdif_ctrl1_set);
185 mdelay(50);
186
187 /* Program the SmartLCD controller */
188 writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
189
190 writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
191 (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
192 (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
193 (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
194 ®s->hw_lcdif_timing);
195
196 /*
197 * OTM2201A init and configuration sequence.
198 */
199 for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
200 mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
201 if (lcd_regs[i].delay)
202 mdelay(lcd_regs[i].delay);
203 }
204 /* Turn on Framebuffer Upload Mode */
205 mxsfb_write_byte(0x22, 0);
206
207 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
208 ®s->hw_lcdif_ctrl_set);
209 }
210 #endif
211
board_init(void)212 int board_init(void)
213 {
214 /* Adress of boot parameters */
215 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
216
217 /* Turn on PWM backlight */
218 gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
219
220 return 0;
221 }
222
board_eth_init(struct bd_info * bis)223 int board_eth_init(struct bd_info *bis)
224 {
225 usb_eth_initialize(bis);
226 return 0;
227 }
228