1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #include <common.h>
7 #include <adc.h>
8 #include <log.h>
9 #include <net.h>
10 #include <asm/arch/stm32.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/global_data.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <bootm.h>
16 #include <clk.h>
17 #include <config.h>
18 #include <dm.h>
19 #include <dm/device.h>
20 #include <dm/uclass.h>
21 #include <env.h>
22 #include <env_internal.h>
23 #include <g_dnl.h>
24 #include <generic-phy.h>
25 #include <hang.h>
26 #include <i2c.h>
27 #include <i2c_eeprom.h>
28 #include <init.h>
29 #include <led.h>
30 #include <memalign.h>
31 #include <misc.h>
32 #include <mtd.h>
33 #include <mtd_node.h>
34 #include <netdev.h>
35 #include <phy.h>
36 #include <linux/bitops.h>
37 #include <linux/delay.h>
38 #include <power/regulator.h>
39 #include <remoteproc.h>
40 #include <reset.h>
41 #include <syscon.h>
42 #include <usb.h>
43 #include <usb/dwc2_udc.h>
44 #include <watchdog.h>
45 #include "../../st/common/stpmic1.h"
46
47 /* SYSCFG registers */
48 #define SYSCFG_BOOTR 0x00
49 #define SYSCFG_PMCSETR 0x04
50 #define SYSCFG_IOCTRLSETR 0x18
51 #define SYSCFG_ICNR 0x1C
52 #define SYSCFG_CMPCR 0x20
53 #define SYSCFG_CMPENSETR 0x24
54 #define SYSCFG_PMCCLRR 0x44
55
56 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
57 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
58
59 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
60 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
61 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
62 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
63 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
64
65 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
66 #define SYSCFG_CMPCR_READY BIT(8)
67
68 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
69
70 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
71 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
72
73 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
74
75 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
76 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
77 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
78 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
79
80 /*
81 * Get a global data pointer
82 */
83 DECLARE_GLOBAL_DATA_PTR;
84
85 #define KS_CCR 0x08
86 #define KS_CCR_EEPROM BIT(9)
87 #define KS_BE0 BIT(12)
88 #define KS_BE1 BIT(13)
89
setup_mac_address(void)90 int setup_mac_address(void)
91 {
92 unsigned char enetaddr[6];
93 bool skip_eth0 = false;
94 bool skip_eth1 = false;
95 struct udevice *dev;
96 int off, ret;
97
98 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
99 if (ret) /* ethaddr is already set */
100 skip_eth0 = true;
101
102 off = fdt_path_offset(gd->fdt_blob, "ethernet1");
103 if (off < 0) {
104 /* ethernet1 is not present in the system */
105 skip_eth1 = true;
106 goto out_set_ethaddr;
107 }
108
109 ret = eth_env_get_enetaddr("eth1addr", enetaddr);
110 if (ret) {
111 /* eth1addr is already set */
112 skip_eth1 = true;
113 goto out_set_ethaddr;
114 }
115
116 ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
117 if (ret)
118 goto out_set_ethaddr;
119
120 /*
121 * KS8851 with EEPROM may use custom MAC from EEPROM, read
122 * out the KS8851 CCR register to determine whether EEPROM
123 * is present. If EEPROM is present, it must contain valid
124 * MAC address.
125 */
126 u32 reg, ccr;
127 reg = fdt_get_base_address(gd->fdt_blob, off);
128 if (!reg)
129 goto out_set_ethaddr;
130
131 writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
132 ccr = readw(reg);
133 if (ccr & KS_CCR_EEPROM) {
134 skip_eth1 = true;
135 goto out_set_ethaddr;
136 }
137
138 out_set_ethaddr:
139 if (skip_eth0 && skip_eth1)
140 return 0;
141
142 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
143 if (off < 0) {
144 printf("%s: No eeprom0 path offset\n", __func__);
145 return off;
146 }
147
148 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
149 if (ret) {
150 printf("Cannot find EEPROM!\n");
151 return ret;
152 }
153
154 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
155 if (ret) {
156 printf("Error reading configuration EEPROM!\n");
157 return ret;
158 }
159
160 if (is_valid_ethaddr(enetaddr)) {
161 if (!skip_eth0)
162 eth_env_set_enetaddr("ethaddr", enetaddr);
163
164 enetaddr[5]++;
165 if (!skip_eth1)
166 eth_env_set_enetaddr("eth1addr", enetaddr);
167 }
168
169 return 0;
170 }
171
checkboard(void)172 int checkboard(void)
173 {
174 char *mode;
175 const char *fdt_compat;
176 int fdt_compat_len;
177
178 if (IS_ENABLED(CONFIG_TFABOOT))
179 mode = "trusted";
180 else
181 mode = "basic";
182
183 printf("Board: stm32mp1 in %s mode", mode);
184 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
185 &fdt_compat_len);
186 if (fdt_compat && fdt_compat_len)
187 printf(" (%s)", fdt_compat);
188 puts("\n");
189
190 return 0;
191 }
192
193 #ifdef CONFIG_BOARD_EARLY_INIT_F
194 static u8 brdcode __section("data");
195 static u8 ddr3code __section("data");
196 static u8 somcode __section("data");
197 static u32 opp_voltage_mv __section(".data");
198
board_get_coding_straps(void)199 static void board_get_coding_straps(void)
200 {
201 struct gpio_desc gpio[4];
202 ofnode node;
203 int i, ret;
204
205 node = ofnode_path("/config");
206 if (!ofnode_valid(node)) {
207 printf("%s: no /config node?\n", __func__);
208 return;
209 }
210
211 brdcode = 0;
212 ddr3code = 0;
213 somcode = 0;
214
215 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
216 gpio, ARRAY_SIZE(gpio),
217 GPIOD_IS_IN);
218 for (i = 0; i < ret; i++)
219 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
220
221 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
222 gpio, ARRAY_SIZE(gpio),
223 GPIOD_IS_IN);
224 for (i = 0; i < ret; i++)
225 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
226
227 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
228 gpio, ARRAY_SIZE(gpio),
229 GPIOD_IS_IN);
230 for (i = 0; i < ret; i++)
231 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
232
233 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
234 somcode, ddr3code, brdcode);
235 }
236
board_stm32mp1_ddr_config_name_match(struct udevice * dev,const char * name)237 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
238 const char *name)
239 {
240 if (ddr3code == 1 &&
241 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
242 return 0;
243
244 if (ddr3code == 2 &&
245 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
246 return 0;
247
248 if (ddr3code == 3 &&
249 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
250 return 0;
251
252 return -EINVAL;
253 }
254
board_vddcore_init(u32 voltage_mv)255 void board_vddcore_init(u32 voltage_mv)
256 {
257 if (IS_ENABLED(CONFIG_SPL_BUILD))
258 opp_voltage_mv = voltage_mv;
259 }
260
board_early_init_f(void)261 int board_early_init_f(void)
262 {
263 if (IS_ENABLED(CONFIG_SPL_BUILD))
264 stpmic1_init(opp_voltage_mv);
265 board_get_coding_straps();
266
267 return 0;
268 }
269
270 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)271 int board_fit_config_name_match(const char *name)
272 {
273 const char *compat;
274 char test[128];
275
276 compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
277
278 snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
279 compat, somcode, brdcode);
280
281 if (!strcmp(name, test))
282 return 0;
283
284 return -EINVAL;
285 }
286 #endif
287 #endif
288
board_key_check(void)289 static void board_key_check(void)
290 {
291 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
292 ofnode node;
293 struct gpio_desc gpio;
294 enum forced_boot_mode boot_mode = BOOT_NORMAL;
295
296 node = ofnode_path("/config");
297 if (!ofnode_valid(node)) {
298 debug("%s: no /config node?\n", __func__);
299 return;
300 }
301 #ifdef CONFIG_FASTBOOT
302 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
303 &gpio, GPIOD_IS_IN)) {
304 debug("%s: could not find a /config/st,fastboot-gpios\n",
305 __func__);
306 } else {
307 if (dm_gpio_get_value(&gpio)) {
308 puts("Fastboot key pressed, ");
309 boot_mode = BOOT_FASTBOOT;
310 }
311
312 dm_gpio_free(NULL, &gpio);
313 }
314 #endif
315 #ifdef CONFIG_CMD_STM32PROG
316 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
317 &gpio, GPIOD_IS_IN)) {
318 debug("%s: could not find a /config/st,stm32prog-gpios\n",
319 __func__);
320 } else {
321 if (dm_gpio_get_value(&gpio)) {
322 puts("STM32Programmer key pressed, ");
323 boot_mode = BOOT_STM32PROG;
324 }
325 dm_gpio_free(NULL, &gpio);
326 }
327 #endif
328
329 if (boot_mode != BOOT_NORMAL) {
330 puts("entering download mode...\n");
331 clrsetbits_le32(TAMP_BOOT_CONTEXT,
332 TAMP_BOOT_FORCED_MASK,
333 boot_mode);
334 }
335 #endif
336 }
337
338 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
339
340 #include <usb/dwc2_udc.h>
g_dnl_board_usb_cable_connected(void)341 int g_dnl_board_usb_cable_connected(void)
342 {
343 struct udevice *dwc2_udc_otg;
344 int ret;
345
346 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
347 DM_DRIVER_GET(dwc2_udc_otg),
348 &dwc2_udc_otg);
349 if (!ret)
350 debug("dwc2_udc_otg init failed\n");
351
352 return dwc2_udc_B_session_valid(dwc2_udc_otg);
353 }
354
355 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
356 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
357
g_dnl_bind_fixup(struct usb_device_descriptor * dev,const char * name)358 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
359 {
360 if (!strcmp(name, "usb_dnl_dfu"))
361 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
362 else if (!strcmp(name, "usb_dnl_fastboot"))
363 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
364 &dev->idProduct);
365 else
366 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
367
368 return 0;
369 }
370
371 #endif /* CONFIG_USB_GADGET */
372
373 #ifdef CONFIG_LED
get_led(struct udevice ** dev,char * led_string)374 static int get_led(struct udevice **dev, char *led_string)
375 {
376 char *led_name;
377 int ret;
378
379 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
380 if (!led_name) {
381 pr_debug("%s: could not find %s config string\n",
382 __func__, led_string);
383 return -ENOENT;
384 }
385 ret = led_get_by_label(led_name, dev);
386 if (ret) {
387 debug("%s: get=%d\n", __func__, ret);
388 return ret;
389 }
390
391 return 0;
392 }
393
setup_led(enum led_state_t cmd)394 static int setup_led(enum led_state_t cmd)
395 {
396 struct udevice *dev;
397 int ret;
398
399 ret = get_led(&dev, "u-boot,boot-led");
400 if (ret)
401 return ret;
402
403 ret = led_set_state(dev, cmd);
404 return ret;
405 }
406 #endif
407
led_error_blink(u32 nb_blink)408 static void __maybe_unused led_error_blink(u32 nb_blink)
409 {
410 #ifdef CONFIG_LED
411 int ret;
412 struct udevice *led;
413 u32 i;
414 #endif
415
416 if (!nb_blink)
417 return;
418
419 #ifdef CONFIG_LED
420 ret = get_led(&led, "u-boot,error-led");
421 if (!ret) {
422 /* make u-boot,error-led blinking */
423 /* if U32_MAX and 125ms interval, for 17.02 years */
424 for (i = 0; i < 2 * nb_blink; i++) {
425 led_set_state(led, LEDST_TOGGLE);
426 mdelay(125);
427 WATCHDOG_RESET();
428 }
429 }
430 #endif
431
432 /* infinite: the boot process must be stopped */
433 if (nb_blink == U32_MAX)
434 hang();
435 }
436
sysconf_init(void)437 static void sysconf_init(void)
438 {
439 #ifndef CONFIG_TFABOOT
440 u8 *syscfg;
441 #ifdef CONFIG_DM_REGULATOR
442 struct udevice *pwr_dev;
443 struct udevice *pwr_reg;
444 struct udevice *dev;
445 int ret;
446 u32 otp = 0;
447 #endif
448 u32 bootr;
449
450 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
451
452 /* interconnect update : select master using the port 1 */
453 /* LTDC = AXI_M9 */
454 /* GPU = AXI_M8 */
455 /* today information is hardcoded in U-Boot */
456 writel(BIT(9), syscfg + SYSCFG_ICNR);
457
458 /* disable Pull-Down for boot pin connected to VDD */
459 bootr = readl(syscfg + SYSCFG_BOOTR);
460 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
461 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
462 writel(bootr, syscfg + SYSCFG_BOOTR);
463
464 #ifdef CONFIG_DM_REGULATOR
465 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
466 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
467 * The customer will have to disable this for low frequencies
468 * or if AFMUX is selected but the function not used, typically for
469 * TRACE. Otherwise, impact on power consumption.
470 *
471 * WARNING:
472 * enabling High Speed mode while VDD>2.7V
473 * with the OTP product_below_2v5 (OTP 18, BIT 13)
474 * erroneously set to 1 can damage the IC!
475 * => U-Boot set the register only if VDD < 2.7V (in DT)
476 * but this value need to be consistent with board design
477 */
478 ret = uclass_get_device_by_driver(UCLASS_PMIC,
479 DM_DRIVER_GET(stm32mp_pwr_pmic),
480 &pwr_dev);
481 if (!ret) {
482 ret = uclass_get_device_by_driver(UCLASS_MISC,
483 DM_DRIVER_GET(stm32mp_bsec),
484 &dev);
485 if (ret) {
486 pr_err("Can't find stm32mp_bsec driver\n");
487 return;
488 }
489
490 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
491 if (ret > 0)
492 otp = otp & BIT(13);
493
494 /* get VDD = vdd-supply */
495 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
496 &pwr_reg);
497
498 /* check if VDD is Low Voltage */
499 if (!ret) {
500 if (regulator_get_value(pwr_reg) < 2700000) {
501 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
502 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
503 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
504 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
505 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
506 syscfg + SYSCFG_IOCTRLSETR);
507
508 if (!otp)
509 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
510 } else {
511 if (otp)
512 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
513 }
514 } else {
515 debug("VDD unknown");
516 }
517 }
518 #endif
519
520 /* activate automatic I/O compensation
521 * warning: need to ensure CSI enabled and ready in clock driver
522 */
523 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
524
525 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
526 ;
527 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
528 #endif
529 }
530
board_init_fmc2(void)531 static void board_init_fmc2(void)
532 {
533 #define STM32_FMC2_BCR1 0x0
534 #define STM32_FMC2_BTR1 0x4
535 #define STM32_FMC2_BWTR1 0x104
536 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
537 #define STM32_FMC2_BCRx_FMCEN BIT(31)
538 #define STM32_FMC2_BCRx_WREN BIT(12)
539 #define STM32_FMC2_BCRx_RSVD BIT(7)
540 #define STM32_FMC2_BCRx_FACCEN BIT(6)
541 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
542 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
543 #define STM32_FMC2_BCRx_MUXEN BIT(1)
544 #define STM32_FMC2_BCRx_MBKEN BIT(0)
545 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
546 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
547 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
548 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
549 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
550 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
551
552 #define RCC_MP_AHB6RSTCLRR 0x218
553 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
554 #define RCC_MP_AHB6ENSETR 0x19c
555 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
556
557 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
558 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
559 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
560 STM32_FMC2_BCRx_MBKEN;
561 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
562 STM32_FMC2_BTRx_BUSTURN(2) |
563 STM32_FMC2_BTRx_DATAST(0x22) |
564 STM32_FMC2_BTRx_ADDHLD(2) |
565 STM32_FMC2_BTRx_ADDSET(2);
566
567 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
568 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
569 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
570
571 /* KS8851-16MLL -- Muxed mode */
572 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
573 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
574 /* AS7C34098 SRAM on X11 -- Muxed mode */
575 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
576 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
577
578 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
579 }
580
581 /* board dependent setup after realloc */
board_init(void)582 int board_init(void)
583 {
584 /* address of boot parameters */
585 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
586
587 if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
588 gpio_hog_probe_all();
589
590 board_key_check();
591
592 #ifdef CONFIG_DM_REGULATOR
593 regulators_enable_boot_on(_DEBUG);
594 #endif
595
596 sysconf_init();
597
598 board_init_fmc2();
599
600 if (CONFIG_IS_ENABLED(LED))
601 led_default_state();
602
603 return 0;
604 }
605
board_late_init(void)606 int board_late_init(void)
607 {
608 char *boot_device;
609 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
610 const void *fdt_compat;
611 int fdt_compat_len;
612
613 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
614 &fdt_compat_len);
615 if (fdt_compat && fdt_compat_len) {
616 if (strncmp(fdt_compat, "st,", 3) != 0)
617 env_set("board_name", fdt_compat);
618 else
619 env_set("board_name", fdt_compat + 3);
620 }
621 #endif
622
623 /* Check the boot-source to disable bootdelay */
624 boot_device = env_get("boot_device");
625 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
626 env_set("bootdelay", "0");
627
628 #ifdef CONFIG_BOARD_EARLY_INIT_F
629 env_set_ulong("dh_som_rev", somcode);
630 env_set_ulong("dh_board_rev", brdcode);
631 env_set_ulong("dh_ddr3_code", ddr3code);
632 #endif
633
634 return 0;
635 }
636
board_quiesce_devices(void)637 void board_quiesce_devices(void)
638 {
639 #ifdef CONFIG_LED
640 setup_led(LEDST_OFF);
641 #endif
642 }
643
644 /* eth init function : weak called in eqos driver */
board_interface_eth_init(struct udevice * dev,phy_interface_t interface_type)645 int board_interface_eth_init(struct udevice *dev,
646 phy_interface_t interface_type)
647 {
648 u8 *syscfg;
649 u32 value;
650 bool eth_clk_sel_reg = false;
651 bool eth_ref_clk_sel_reg = false;
652
653 /* Gigabit Ethernet 125MHz clock selection. */
654 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
655
656 /* Ethernet 50Mhz RMII clock selection */
657 eth_ref_clk_sel_reg =
658 dev_read_bool(dev, "st,eth_ref_clk_sel");
659
660 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
661
662 if (!syscfg)
663 return -ENODEV;
664
665 switch (interface_type) {
666 case PHY_INTERFACE_MODE_MII:
667 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
668 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
669 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
670 break;
671 case PHY_INTERFACE_MODE_GMII:
672 if (eth_clk_sel_reg)
673 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
674 SYSCFG_PMCSETR_ETH_CLK_SEL;
675 else
676 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
677 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
678 break;
679 case PHY_INTERFACE_MODE_RMII:
680 if (eth_ref_clk_sel_reg)
681 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
682 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
683 else
684 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
685 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
686 break;
687 case PHY_INTERFACE_MODE_RGMII:
688 case PHY_INTERFACE_MODE_RGMII_ID:
689 case PHY_INTERFACE_MODE_RGMII_RXID:
690 case PHY_INTERFACE_MODE_RGMII_TXID:
691 if (eth_clk_sel_reg)
692 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
693 SYSCFG_PMCSETR_ETH_CLK_SEL;
694 else
695 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
696 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
697 break;
698 default:
699 debug("%s: Do not manage %d interface\n",
700 __func__, interface_type);
701 /* Do not manage others interfaces */
702 return -EINVAL;
703 }
704
705 /* clear and set ETH configuration bits */
706 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
707 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
708 syscfg + SYSCFG_PMCCLRR);
709 writel(value, syscfg + SYSCFG_PMCSETR);
710
711 return 0;
712 }
713
714 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)715 int ft_board_setup(void *blob, struct bd_info *bd)
716 {
717 return 0;
718 }
719 #endif
720
board_copro_image_process(ulong fw_image,size_t fw_size)721 static void board_copro_image_process(ulong fw_image, size_t fw_size)
722 {
723 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
724
725 if (!rproc_is_initialized())
726 if (rproc_init()) {
727 printf("Remote Processor %d initialization failed\n",
728 id);
729 return;
730 }
731
732 ret = rproc_load(id, fw_image, fw_size);
733 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
734 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
735
736 if (!ret) {
737 rproc_start(id);
738 env_set("copro_state", "booted");
739 }
740 }
741
742 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
743