1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Board functions for EETS PDU001 board
6 *
7 * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
8 *
9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
10 */
11
12 #include <common.h>
13 #include <env.h>
14 #include <errno.h>
15 #include <init.h>
16 #include <log.h>
17 #include <spl.h>
18 #include <i2c.h>
19 #include <watchdog.h>
20 #include <debug_uart.h>
21 #include <asm/global_data.h>
22 #include <dm/ofnode.h>
23 #include <power/pmic.h>
24 #include <power/regulator.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/hardware.h>
27 #include <asm/arch/omap.h>
28 #include <asm/arch/ddr_defs.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/mmc_host_def.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/arch/mem.h>
34 #include <asm/io.h>
35 #include <asm/emif.h>
36 #include <asm/gpio.h>
37 #include "board.h"
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #define I2C_ADDR_NODE_ID 0x50
42 #define I2C_REG_NODE_ID_BASE 0xfa
43 #define NODE_ID_BYTE_COUNT 6
44
45 #define I2C_ADDR_LEDS 0x60
46 #define I2C_REG_RUN_LED 0x06
47 #define RUN_LED_OFF 0x0
48 #define RUN_LED_RED 0x1
49 #define RUN_LED_GREEN (0x1 << 2)
50
51 #define VDD_MPU_REGULATOR "regulator@2"
52 #define VDD_CORE_REGULATOR "regulator@3"
53 #define DEFAULT_CORE_VOLTAGE 1137500
54
55 /*
56 * boot device save register
57 * -------------------------
58 * The boot device can be quired by 'spl_boot_device()' in
59 * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
60 * environment here. In turn 'spl_boot_device' can't be called in
61 * 'board_late_init' which allows writing to u-boot environment.
62 * To get the boot device from 'am33xx_spl_board_init' to
63 * 'board_late_init' we therefore use a scratch register from the RTC.
64 */
65 #define CONFIG_SYS_RTC_SCRATCH0 0x60
66 #define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
67
68 #ifdef CONFIG_SPL_BUILD
save_boot_device(void)69 static void save_boot_device(void)
70 {
71 *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
72 }
73 #endif
74
boot_device(void)75 u32 boot_device(void)
76 {
77 return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
78 }
79
80 /* Store the boot device in the environment variable 'boot_device' */
env_set_boot_device(void)81 static void env_set_boot_device(void)
82 {
83 switch (boot_device()) {
84 case BOOT_DEVICE_MMC1: {
85 env_set("boot_device", "emmc");
86 break;
87 }
88 case BOOT_DEVICE_MMC2: {
89 env_set("boot_device", "sdcard");
90 break;
91 }
92 default: {
93 env_set("boot_device", "unknown");
94 break;
95 }
96 }
97 }
98
set_run_led(struct udevice * dev)99 static void set_run_led(struct udevice *dev)
100 {
101 int val = RUN_LED_OFF;
102
103 if (IS_ENABLED(CONFIG_RUN_LED_RED))
104 val = RUN_LED_RED;
105 else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
106 val = RUN_LED_GREEN;
107
108 dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
109 }
110
111 /* Set 'serial#' to the EUI-48 value of board node ID chip */
env_set_serial(struct udevice * dev)112 static void env_set_serial(struct udevice *dev)
113 {
114 int val;
115 char serial[2 * NODE_ID_BYTE_COUNT + 1];
116 int n;
117
118 for (n = 0; n < sizeof(serial); n += 2) {
119 val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
120 sprintf(serial + n, "%02X", val);
121 }
122 serial[2 * NODE_ID_BYTE_COUNT] = '\0';
123 env_set("serial#", serial);
124 }
125
set_mpu_and_core_voltage(void)126 static void set_mpu_and_core_voltage(void)
127 {
128 int mpu_vdd;
129 int sil_rev;
130 struct udevice *dev;
131 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
132
133 /*
134 * The PDU001 (more precisely the computing module m2) uses a
135 * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
136 * voltage of 1.1375V. For MPU voltage we need to switch based on
137 * the frequency we are running at.
138 */
139
140 /*
141 * Depending on MPU clock and PG we will need a different VDD
142 * to drive at that speed.
143 */
144 sil_rev = readl(&cdev->deviceid) >> 28;
145 mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
146
147 /* first update the MPU voltage */
148 if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
149 if (regulator_set_value(dev, mpu_vdd))
150 debug("failed to set MPU voltage\n");
151 } else {
152 debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
153 }
154
155 /* second update the CORE voltage */
156 if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
157 if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
158 debug("failed to set CORE voltage\n");
159 } else {
160 debug("invalid CORE voltage ragulator %s\n",
161 VDD_CORE_REGULATOR);
162 }
163 }
164
165 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
166 static const struct ddr_data ddr2_data = {
167 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
168 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
169 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
170 };
171
172 static const struct cmd_control ddr2_cmd_ctrl_data = {
173 .cmd0csratio = MT47H128M16RT25E_RATIO,
174 .cmd1csratio = MT47H128M16RT25E_RATIO,
175 .cmd2csratio = MT47H128M16RT25E_RATIO,
176 };
177
178 static const struct emif_regs ddr2_emif_reg_data = {
179 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
180 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
181 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
182 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
183 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
184 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
185 };
186
187 #define OSC (V_OSCK / 1000000)
188 const struct dpll_params dpll_ddr = {
189 266, OSC - 1, 1, -1, -1, -1, -1};
190 const struct dpll_params dpll_ddr_evm_sk = {
191 303, OSC - 1, 1, -1, -1, -1, -1};
192 const struct dpll_params dpll_ddr_bone_black = {
193 400, OSC - 1, 1, -1, -1, -1, -1};
194
am33xx_spl_board_init(void)195 void am33xx_spl_board_init(void)
196 {
197 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
198
199 /* Get the frequency */
200 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
201
202 /* Set CORE Frequencies to OPP100 */
203 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
204
205 /* Set MPU Frequency to what we detected now that voltages are set */
206 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
207
208 /* save boot device for later use by 'board_late_init' */
209 save_boot_device();
210 }
211
get_dpll_ddr_params(void)212 const struct dpll_params *get_dpll_ddr_params(void)
213 {
214 enable_i2c0_pin_mux();
215
216 return &dpll_ddr;
217 }
218
set_mux_conf_regs(void)219 void set_mux_conf_regs(void)
220 {
221 /* done first by the ROM and afterwards by the pin controller driver */
222 enable_i2c0_pin_mux();
223 }
224
225 const struct ctrl_ioregs ioregs = {
226 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
227 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
228 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
229 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
230 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
231 };
232
sdram_init(void)233 void sdram_init(void)
234 {
235 config_ddr(266, &ioregs, &ddr2_data,
236 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
237 }
238 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
239
240 #ifdef CONFIG_DEBUG_UART
board_debug_uart_init(void)241 void board_debug_uart_init(void)
242 {
243 /* done by pin controller driver if not debugging */
244 enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
245 }
246 #endif
247
248 /*
249 * Basic board specific setup. Pinmux has been handled already.
250 */
board_init(void)251 int board_init(void)
252 {
253 #ifdef CONFIG_HW_WATCHDOG
254 hw_watchdog_init();
255 #endif
256
257 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
258 return 0;
259 }
260
261 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)262 int board_late_init(void)
263 {
264 struct udevice *dev;
265
266 set_mpu_and_core_voltage();
267 env_set_boot_device();
268
269 /* second I2C bus connects to node ID and front panel LED chip */
270 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
271 set_run_led(dev);
272 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
273 env_set_serial(dev);
274
275 return 0;
276 }
277 #endif
278