1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Eukréa Electromatique
4 * Author: Eric Bénard <eric@eukrea.com>
5 * Fabio Estevam <fabio.estevam@freescale.com>
6 * Jon Nettleton <jon.nettleton@gmail.com>
7 *
8 * based on sabresd.c which is :
9 * Copyright (C) 2012 Freescale Semiconductor, Inc.
10 * and on hummingboard.c which is :
11 * Copyright (C) 2013 SolidRun ltd.
12 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
13 */
14
15 #include <common.h>
16 #include <init.h>
17 #include <net.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/iomux.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/global_data.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <asm/gpio.h>
27 #include <asm/mach-imx/iomux-v3.h>
28 #include <asm/mach-imx/boot_mode.h>
29 #include <asm/mach-imx/mxc_i2c.h>
30 #include <asm/mach-imx/spi.h>
31 #include <asm/mach-imx/video.h>
32 #include <i2c.h>
33 #include <input.h>
34 #include <mmc.h>
35 #include <fsl_esdhc_imx.h>
36 #include <miiphy.h>
37 #include <netdev.h>
38 #include <asm/arch/mxc_hdmi.h>
39 #include <asm/arch/crm_regs.h>
40 #include <linux/fb.h>
41 #include <ipu_pixfmt.h>
42 #include <asm/io.h>
43
44 DECLARE_GLOBAL_DATA_PTR;
45
46 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
48 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
51 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53
54 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
55 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
56 PAD_CTL_HYS)
57
58 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
59 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
60
61 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
62 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
63
64 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
66
67 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
69 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
70
71 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
72 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
73
74 static int board_type = -1;
75 #define BOARD_IS_MARSBOARD 0
76 #define BOARD_IS_RIOTBOARD 1
77
dram_init(void)78 int dram_init(void)
79 {
80 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
81
82 return 0;
83 }
84
85 static iomux_v3_cfg_t const uart2_pads[] = {
86 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
87 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
88 };
89
setup_iomux_uart(void)90 static void setup_iomux_uart(void)
91 {
92 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
93 }
94
95 iomux_v3_cfg_t const enet_pads[] = {
96 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 /* GPIO16 -> AR8035 25MHz */
99 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
100 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
101 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
107 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
108 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
110 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
111 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
113 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
114 /* AR8035 PHY Reset */
115 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
116 /* AR8035 PHY Interrupt */
117 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 };
119
setup_iomux_enet(void)120 static void setup_iomux_enet(void)
121 {
122 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
123
124 /* Reset AR8035 PHY */
125 gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
126 mdelay(2);
127 gpio_set_value(IMX_GPIO_NR(3, 31), 1);
128 }
129
mx6_rgmii_rework(struct phy_device * phydev)130 int mx6_rgmii_rework(struct phy_device *phydev)
131 {
132 /* from linux/arch/arm/mach-imx/mach-imx6q.c :
133 * Ar803x phy SmartEEE feature cause link status generates glitch,
134 * which cause ethernet link down/up issue, so disable SmartEEE
135 */
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
138 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
139
140 return 0;
141 }
142
board_phy_config(struct phy_device * phydev)143 int board_phy_config(struct phy_device *phydev)
144 {
145 mx6_rgmii_rework(phydev);
146
147 if (phydev->drv->config)
148 phydev->drv->config(phydev);
149
150 return 0;
151 }
152
153 iomux_v3_cfg_t const usdhc2_pads[] = {
154 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
155 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
161 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
162 };
163
164 iomux_v3_cfg_t const usdhc3_pads[] = {
165 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
166 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
167 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
168 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
169 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 };
172
173 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
174 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
175 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
176 };
177
178 iomux_v3_cfg_t const usdhc4_pads[] = {
179 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
180 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
183 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185 /* eMMC RST */
186 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
187 };
188
189 #ifdef CONFIG_FSL_ESDHC_IMX
190 struct fsl_esdhc_cfg usdhc_cfg[3] = {
191 {USDHC2_BASE_ADDR},
192 {USDHC3_BASE_ADDR},
193 {USDHC4_BASE_ADDR},
194 };
195
196 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
197 #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
198
board_mmc_getcd(struct mmc * mmc)199 int board_mmc_getcd(struct mmc *mmc)
200 {
201 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
202 int ret = 0;
203
204 switch (cfg->esdhc_base) {
205 case USDHC2_BASE_ADDR:
206 ret = !gpio_get_value(USDHC2_CD_GPIO);
207 break;
208 case USDHC3_BASE_ADDR:
209 if (board_type == BOARD_IS_RIOTBOARD)
210 ret = !gpio_get_value(USDHC3_CD_GPIO);
211 else if (board_type == BOARD_IS_MARSBOARD)
212 ret = 1; /* eMMC/uSDHC3 is always present */
213 break;
214 case USDHC4_BASE_ADDR:
215 ret = 1; /* eMMC/uSDHC4 is always present */
216 break;
217 }
218
219 return ret;
220 }
221
board_mmc_init(struct bd_info * bis)222 int board_mmc_init(struct bd_info *bis)
223 {
224 int ret;
225 int i;
226
227 /*
228 * According to the board_mmc_init() the following map is done:
229 * (U-Boot device node) (Physical Port)
230 * ** RiOTboard :
231 * mmc0 SDCard slot (bottom)
232 * mmc1 uSDCard slot (top)
233 * mmc2 eMMC
234 * ** MarSBoard :
235 * mmc0 uSDCard slot (bottom)
236 * mmc1 eMMC
237 */
238 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
239 switch (i) {
240 case 0:
241 imx_iomux_v3_setup_multiple_pads(
242 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
243 gpio_direction_input(USDHC2_CD_GPIO);
244 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
245 usdhc_cfg[0].max_bus_width = 4;
246 break;
247 case 1:
248 imx_iomux_v3_setup_multiple_pads(
249 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
250 if (board_type == BOARD_IS_RIOTBOARD) {
251 imx_iomux_v3_setup_multiple_pads(
252 riotboard_usdhc3_pads,
253 ARRAY_SIZE(riotboard_usdhc3_pads));
254 gpio_direction_input(USDHC3_CD_GPIO);
255 } else {
256 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
257 udelay(250);
258 gpio_set_value(IMX_GPIO_NR(7, 8), 1);
259 }
260 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
261 usdhc_cfg[1].max_bus_width = 4;
262 break;
263 case 2:
264 imx_iomux_v3_setup_multiple_pads(
265 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
266 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
267 usdhc_cfg[2].max_bus_width = 4;
268 gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
269 udelay(250);
270 gpio_set_value(IMX_GPIO_NR(6, 8), 1);
271 break;
272 default:
273 printf("Warning: you configured more USDHC controllers"
274 "(%d) then supported by the board (%d)\n",
275 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
276 return -EINVAL;
277 }
278
279 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
280 if (ret)
281 return ret;
282 }
283
284 return 0;
285 }
286 #endif
287
288 #ifdef CONFIG_MXC_SPI
289 iomux_v3_cfg_t const ecspi1_pads[] = {
290 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
291 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
292 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
293 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
294 };
295
board_spi_cs_gpio(unsigned bus,unsigned cs)296 int board_spi_cs_gpio(unsigned bus, unsigned cs)
297 {
298 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
299 }
300
setup_spi(void)301 static void setup_spi(void)
302 {
303 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
304 }
305 #endif
306
307 struct i2c_pads_info i2c_pad_info1 = {
308 .scl = {
309 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
310 | MUX_PAD_CTRL(I2C_PAD_CTRL),
311 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
312 | MUX_PAD_CTRL(I2C_PAD_CTRL),
313 .gp = IMX_GPIO_NR(5, 27)
314 },
315 .sda = {
316 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
317 | MUX_PAD_CTRL(I2C_PAD_CTRL),
318 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
319 | MUX_PAD_CTRL(I2C_PAD_CTRL),
320 .gp = IMX_GPIO_NR(5, 26)
321 }
322 };
323
324 struct i2c_pads_info i2c_pad_info2 = {
325 .scl = {
326 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
327 | MUX_PAD_CTRL(I2C_PAD_CTRL),
328 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
329 | MUX_PAD_CTRL(I2C_PAD_CTRL),
330 .gp = IMX_GPIO_NR(4, 12)
331 },
332 .sda = {
333 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
334 | MUX_PAD_CTRL(I2C_PAD_CTRL),
335 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
336 | MUX_PAD_CTRL(I2C_PAD_CTRL),
337 .gp = IMX_GPIO_NR(4, 13)
338 }
339 };
340
341 struct i2c_pads_info i2c_pad_info3 = {
342 .scl = {
343 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
344 | MUX_PAD_CTRL(I2C_PAD_CTRL),
345 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
346 | MUX_PAD_CTRL(I2C_PAD_CTRL),
347 .gp = IMX_GPIO_NR(1, 5)
348 },
349 .sda = {
350 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
351 | MUX_PAD_CTRL(I2C_PAD_CTRL),
352 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
353 | MUX_PAD_CTRL(I2C_PAD_CTRL),
354 .gp = IMX_GPIO_NR(1, 6)
355 }
356 };
357
358 iomux_v3_cfg_t const tft_pads_riot[] = {
359 /* LCD_PWR_EN */
360 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
361 /* TOUCH_INT */
362 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
363 /* LED_PWR_EN */
364 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
365 /* BL LEVEL */
366 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
367 };
368
369 iomux_v3_cfg_t const tft_pads_mars[] = {
370 /* LCD_PWR_EN */
371 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
372 /* TOUCH_INT */
373 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
374 /* LED_PWR_EN */
375 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
376 /* BL LEVEL (PWM4) */
377 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
378 };
379
380 #if defined(CONFIG_VIDEO_IPUV3)
381
enable_lvds(struct display_info_t const * dev)382 static void enable_lvds(struct display_info_t const *dev)
383 {
384 struct iomuxc *iomux = (struct iomuxc *)
385 IOMUXC_BASE_ADDR;
386 setbits_le32(&iomux->gpr[2],
387 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
388 /* set backlight level to ON */
389 if (board_type == BOARD_IS_RIOTBOARD)
390 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
391 else if (board_type == BOARD_IS_MARSBOARD)
392 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
393 }
394
disable_lvds(struct display_info_t const * dev)395 static void disable_lvds(struct display_info_t const *dev)
396 {
397 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
398
399 /* set backlight level to OFF */
400 if (board_type == BOARD_IS_RIOTBOARD)
401 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
402 else if (board_type == BOARD_IS_MARSBOARD)
403 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
404
405 clrbits_le32(&iomux->gpr[2],
406 IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
407 }
408
do_enable_hdmi(struct display_info_t const * dev)409 static void do_enable_hdmi(struct display_info_t const *dev)
410 {
411 disable_lvds(dev);
412 imx_enable_hdmi_phy();
413 }
414
detect_i2c(struct display_info_t const * dev)415 static int detect_i2c(struct display_info_t const *dev)
416 {
417 return (0 == i2c_set_bus_num(dev->bus)) &&
418 (0 == i2c_probe(dev->addr));
419 }
420
421 struct display_info_t const displays[] = {{
422 .bus = -1,
423 .addr = 0,
424 .pixfmt = IPU_PIX_FMT_RGB24,
425 .detect = detect_hdmi,
426 .enable = do_enable_hdmi,
427 .mode = {
428 .name = "HDMI",
429 .refresh = 60,
430 .xres = 1024,
431 .yres = 768,
432 .pixclock = 15385,
433 .left_margin = 220,
434 .right_margin = 40,
435 .upper_margin = 21,
436 .lower_margin = 7,
437 .hsync_len = 60,
438 .vsync_len = 10,
439 .sync = FB_SYNC_EXT,
440 .vmode = FB_VMODE_NONINTERLACED
441 } }, {
442 .bus = 2,
443 .addr = 0x1,
444 .pixfmt = IPU_PIX_FMT_LVDS666,
445 .detect = detect_i2c,
446 .enable = enable_lvds,
447 .mode = {
448 .name = "LCD8000-97C",
449 .refresh = 60,
450 .xres = 1024,
451 .yres = 768,
452 .pixclock = 15385,
453 .left_margin = 100,
454 .right_margin = 200,
455 .upper_margin = 10,
456 .lower_margin = 20,
457 .hsync_len = 20,
458 .vsync_len = 8,
459 .sync = FB_SYNC_EXT,
460 .vmode = FB_VMODE_NONINTERLACED
461 } } };
462 size_t display_count = ARRAY_SIZE(displays);
463
setup_display(void)464 static void setup_display(void)
465 {
466 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
467 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
468 int reg;
469
470 enable_ipu_clock();
471 imx_setup_hdmi();
472
473 /* Turn on LDB0, IPU,IPU DI0 clocks */
474 setbits_le32(&mxc_ccm->CCGR3,
475 MXC_CCM_CCGR3_LDB_DI0_MASK);
476
477 /* set LDB0 clk select to 011/011 */
478 clrsetbits_le32(&mxc_ccm->cs2cdr,
479 MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
480 (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
481
482 setbits_le32(&mxc_ccm->cscmr2,
483 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
484
485 setbits_le32(&mxc_ccm->chsccdr,
486 (CHSCCDR_CLK_SEL_LDB_DI0
487 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
488
489 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
490 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
491 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
492 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
493 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
494 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
495 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
496 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
497 writel(reg, &iomux->gpr[2]);
498
499 clrsetbits_le32(&iomux->gpr[3],
500 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
501 IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
502 IOMUXC_GPR3_MUX_SRC_IPU1_DI0
503 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
504 }
505 #endif /* CONFIG_VIDEO_IPUV3 */
506
507 /*
508 * Do not overwrite the console
509 * Use always serial for U-Boot console
510 */
overwrite_console(void)511 int overwrite_console(void)
512 {
513 return 1;
514 }
515
board_eth_init(struct bd_info * bis)516 int board_eth_init(struct bd_info *bis)
517 {
518 setup_iomux_enet();
519
520 return cpu_eth_init(bis);
521 }
522
board_early_init_f(void)523 int board_early_init_f(void)
524 {
525 u32 cputype = cpu_type(get_cpu_rev());
526
527 switch (cputype) {
528 case MXC_CPU_MX6SOLO:
529 board_type = BOARD_IS_RIOTBOARD;
530 break;
531 case MXC_CPU_MX6D:
532 board_type = BOARD_IS_MARSBOARD;
533 break;
534 }
535
536 setup_iomux_uart();
537
538 if (board_type == BOARD_IS_RIOTBOARD)
539 imx_iomux_v3_setup_multiple_pads(
540 tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
541 else if (board_type == BOARD_IS_MARSBOARD)
542 imx_iomux_v3_setup_multiple_pads(
543 tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
544 #if defined(CONFIG_VIDEO_IPUV3)
545 /* power ON LCD */
546 gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
547 /* touch interrupt is an input */
548 gpio_direction_input(IMX_GPIO_NR(6, 14));
549 /* power ON backlight */
550 gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
551 /* set backlight level to off */
552 if (board_type == BOARD_IS_RIOTBOARD)
553 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
554 else if (board_type == BOARD_IS_MARSBOARD)
555 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
556 setup_display();
557 #endif
558
559 return 0;
560 }
561
board_init(void)562 int board_init(void)
563 {
564 /* address of boot parameters */
565 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
566 /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
567 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
568 /* i2c2 : HDMI EDID */
569 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
570 /* i2c3 : LVDS, Expansion connector */
571 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
572 #ifdef CONFIG_MXC_SPI
573 setup_spi();
574 #endif
575 return 0;
576 }
577
578 #ifdef CONFIG_CMD_BMODE
579 static const struct boot_mode riotboard_boot_modes[] = {
580 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
581 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
582 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
583 {NULL, 0},
584 };
585 static const struct boot_mode marsboard_boot_modes[] = {
586 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
587 {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
588 {NULL, 0},
589 };
590 #endif
591
board_late_init(void)592 int board_late_init(void)
593 {
594 #ifdef CONFIG_CMD_BMODE
595 if (board_type == BOARD_IS_RIOTBOARD)
596 add_board_boot_modes(riotboard_boot_modes);
597 else if (board_type == BOARD_IS_RIOTBOARD)
598 add_board_boot_modes(marsboard_boot_modes);
599 #endif
600
601 return 0;
602 }
603
checkboard(void)604 int checkboard(void)
605 {
606 puts("Board: ");
607 if (board_type == BOARD_IS_MARSBOARD)
608 puts("MarSBoard\n");
609 else if (board_type == BOARD_IS_RIOTBOARD)
610 puts("RIoTboard\n");
611 else
612 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
613
614 return 0;
615 }
616
617 #ifdef CONFIG_SPL_BUILD
618 #include <spl.h>
619
board_init_f(ulong dummy)620 void board_init_f(ulong dummy)
621 {
622 u32 cputype = cpu_type(get_cpu_rev());
623
624 switch (cputype) {
625 case MXC_CPU_MX6SOLO:
626 board_type = BOARD_IS_RIOTBOARD;
627 break;
628 case MXC_CPU_MX6D:
629 board_type = BOARD_IS_MARSBOARD;
630 break;
631 }
632 arch_cpu_init();
633
634 /* setup GP timer */
635 timer_init();
636
637 #ifdef CONFIG_SPL_SERIAL_SUPPORT
638 setup_iomux_uart();
639 preloader_console_init();
640 #endif
641 }
642
board_boot_order(u32 * spl_boot_list)643 void board_boot_order(u32 *spl_boot_list)
644 {
645 spl_boot_list[0] = BOOT_DEVICE_MMC1;
646 }
647
648 /*
649 * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
650 * to pin 3 (ground).
651 */
spl_start_uboot(void)652 int spl_start_uboot(void)
653 {
654 int gpio_key = IMX_GPIO_NR(4, 16);
655
656 gpio_direction_input(gpio_key);
657 if (gpio_get_value(gpio_key) == 0)
658 return 1;
659 else
660 return 0;
661 }
662
663 #endif
664