1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <hwconfig.h>
9 #include <init.h>
10 #include <log.h>
11 #include <vsprintf.h>
12 #include <asm/global_data.h>
13 #include <asm/mmu.h>
14 #include <fsl_ddr_sdram.h>
15 #include <fsl_ddr_dimm_params.h>
16 #include <asm/fsl_law.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20
21 /*
22 * Fixed sdram init -- doesn't use serial presence detect.
23 */
24 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
25 #if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
26 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
27 #endif
28
fixed_sdram(void)29 phys_size_t fixed_sdram(void)
30 {
31 int i;
32 char buf[32];
33 fsl_ddr_cfg_regs_t ddr_cfg_regs;
34 phys_size_t ddr_size;
35 unsigned int lawbar1_target_id;
36 ulong ddr_freq, ddr_freq_mhz;
37
38 ddr_freq = get_ddr_freq(0);
39 ddr_freq_mhz = ddr_freq / 1000000;
40
41 printf("Configuring DDR for %s MT/s data rate\n",
42 strmhz(buf, ddr_freq));
43
44 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
45 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
46 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
47 memcpy(&ddr_cfg_regs,
48 fixed_ddr_parm_0[i].ddr_settings,
49 sizeof(ddr_cfg_regs));
50 break;
51 }
52 }
53
54 if (fixed_ddr_parm_0[i].max_freq == 0)
55 panic("Unsupported DDR data rate %s MT/s data rate\n",
56 strmhz(buf, ddr_freq));
57
58 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
59 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
60 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
61
62 #if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
63 memcpy(&ddr_cfg_regs,
64 fixed_ddr_parm_1[i].ddr_settings,
65 sizeof(ddr_cfg_regs));
66 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
67 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
68 #endif
69
70 /*
71 * setup laws for DDR. If not interleaving, presuming half memory on
72 * DDR1 and the other half on DDR2
73 */
74 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
75 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
76 ddr_size,
77 LAW_TRGT_IF_DDR_INTRLV) < 0) {
78 printf("ERROR setting Local Access Windows for DDR\n");
79 return 0;
80 }
81 } else {
82 #if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
83 /* We require both controllers have identical DIMMs */
84 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
85 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
86 ddr_size / 2,
87 lawbar1_target_id) < 0) {
88 printf("ERROR setting Local Access Windows for DDR\n");
89 return 0;
90 }
91 lawbar1_target_id = LAW_TRGT_IF_DDR_2;
92 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
93 ddr_size / 2,
94 lawbar1_target_id) < 0) {
95 printf("ERROR setting Local Access Windows for DDR\n");
96 return 0;
97 }
98 #else
99 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
100 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
101 ddr_size,
102 lawbar1_target_id) < 0) {
103 printf("ERROR setting Local Access Windows for DDR\n");
104 return 0;
105 }
106 #endif
107 }
108 return ddr_size;
109 }
110
111 struct board_specific_parameters {
112 u32 n_ranks;
113 u32 datarate_mhz_high;
114 u32 clk_adjust;
115 u32 wrlvl_start;
116 u32 cpo;
117 u32 write_data_delay;
118 u32 force_2t;
119 };
120
121 /*
122 * This table contains all valid speeds we want to override with board
123 * specific parameters. datarate_mhz_high values need to be in ascending order
124 * for each n_ranks group.
125 */
126 static const struct board_specific_parameters udimm0[] = {
127 /*
128 * memory controller 0
129 * num| hi| clk| wrlvl | cpo |wrdata|2T
130 * ranks| mhz|adjst| start | |delay |
131 */
132 {4, 850, 4, 6, 0xff, 2, 0},
133 {4, 950, 5, 7, 0xff, 2, 0},
134 {4, 1050, 5, 8, 0xff, 2, 0},
135 {4, 1250, 5, 10, 0xff, 2, 0},
136 {4, 1350, 5, 11, 0xff, 2, 0},
137 {4, 1666, 5, 12, 0xff, 2, 0},
138 {2, 850, 5, 6, 0xff, 2, 0},
139 {2, 1050, 5, 7, 0xff, 2, 0},
140 {2, 1250, 4, 6, 0xff, 2, 0},
141 {2, 1350, 5, 7, 0xff, 2, 0},
142 {2, 1666, 5, 8, 0xff, 2, 0},
143 {1, 1250, 4, 6, 0xff, 2, 0},
144 {1, 1335, 4, 7, 0xff, 2, 0},
145 {1, 1666, 4, 8, 0xff, 2, 0},
146 {}
147 };
148
149 /*
150 * The two slots have slightly different timing. The center values are good
151 * for both slots. We use identical speed tables for them. In future use, if
152 * DIMMs have fewer center values that require two separated tables, copy the
153 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
154 */
155 static const struct board_specific_parameters *udimms[] = {
156 udimm0,
157 udimm0,
158 };
159
160 static const struct board_specific_parameters rdimm0[] = {
161 /*
162 * memory controller 0
163 * num| hi| clk| wrlvl | cpo |wrdata|2T
164 * ranks| mhz|adjst| start | |delay |
165 */
166 {4, 850, 4, 6, 0xff, 2, 0},
167 {4, 950, 5, 7, 0xff, 2, 0},
168 {4, 1050, 5, 8, 0xff, 2, 0},
169 {4, 1250, 5, 10, 0xff, 2, 0},
170 {4, 1350, 5, 11, 0xff, 2, 0},
171 {4, 1666, 5, 12, 0xff, 2, 0},
172 {2, 850, 4, 6, 0xff, 2, 0},
173 {2, 1050, 4, 7, 0xff, 2, 0},
174 {2, 1666, 4, 8, 0xff, 2, 0},
175 {1, 850, 4, 5, 0xff, 2, 0},
176 {1, 950, 4, 7, 0xff, 2, 0},
177 {1, 1666, 4, 8, 0xff, 2, 0},
178 {}
179 };
180
181 /*
182 * The two slots have slightly different timing. See comments above.
183 */
184 static const struct board_specific_parameters *rdimms[] = {
185 rdimm0,
186 rdimm0,
187 };
188
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)189 void fsl_ddr_board_options(memctl_options_t *popts,
190 dimm_params_t *pdimm,
191 unsigned int ctrl_num)
192 {
193 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
194 ulong ddr_freq;
195
196 if (ctrl_num > 1) {
197 printf("Wrong parameter for controller number %d", ctrl_num);
198 return;
199 }
200 if (!pdimm->n_ranks)
201 return;
202
203 if (popts->registered_dimm_en)
204 pbsp = rdimms[ctrl_num];
205 else
206 pbsp = udimms[ctrl_num];
207
208
209 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
210 * freqency and n_banks specified in board_specific_parameters table.
211 */
212 ddr_freq = get_ddr_freq(0) / 1000000;
213 while (pbsp->datarate_mhz_high) {
214 if (pbsp->n_ranks == pdimm->n_ranks) {
215 if (ddr_freq <= pbsp->datarate_mhz_high) {
216 popts->cpo_override = pbsp->cpo;
217 popts->write_data_delay =
218 pbsp->write_data_delay;
219 popts->clk_adjust = pbsp->clk_adjust;
220 popts->wrlvl_start = pbsp->wrlvl_start;
221 popts->twot_en = pbsp->force_2t;
222 goto found;
223 }
224 pbsp_highest = pbsp;
225 }
226 pbsp++;
227 }
228
229 if (pbsp_highest) {
230 printf("Error: board specific timing not found "
231 "for data rate %lu MT/s!\n"
232 "Trying to use the highest speed (%u) parameters\n",
233 ddr_freq, pbsp_highest->datarate_mhz_high);
234 popts->cpo_override = pbsp_highest->cpo;
235 popts->write_data_delay = pbsp_highest->write_data_delay;
236 popts->clk_adjust = pbsp_highest->clk_adjust;
237 popts->wrlvl_start = pbsp_highest->wrlvl_start;
238 popts->twot_en = pbsp_highest->force_2t;
239 } else {
240 panic("DIMM is not supported by this board");
241 }
242 found:
243 /*
244 * Factors to consider for half-strength driver enable:
245 * - number of DIMMs installed
246 */
247 popts->half_strength_driver_enable = 0;
248 /*
249 * Write leveling override
250 */
251 popts->wrlvl_override = 1;
252 popts->wrlvl_sample = 0xf;
253
254 /*
255 * Rtt and Rtt_WR override
256 */
257 popts->rtt_override = 0;
258
259 /* Enable ZQ calibration */
260 popts->zq_en = 1;
261
262 /* DHC_EN =1, ODT = 60 Ohm */
263 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
264 }
265
dram_init(void)266 int dram_init(void)
267 {
268 phys_size_t dram_size;
269
270 puts("Initializing....");
271
272 if (fsl_use_spd()) {
273 puts("using SPD\n");
274 dram_size = fsl_ddr_sdram();
275 } else {
276 puts("using fixed parameters\n");
277 dram_size = fixed_sdram();
278 }
279
280 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
281 dram_size *= 0x100000;
282
283 debug(" DDR: ");
284 gd->ram_size = dram_size;
285
286 return 0;
287 }
288