1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <fdt_support.h>
9 #include <net.h>
10 #include <netdev.h>
11 #include <asm/mmu.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <fsl_ddr_sdram.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
20 #include <malloc.h>
21 #include <fm_eth.h>
22 #include <fsl_mdio.h>
23 #include <miiphy.h>
24 #include <phy.h>
25 #include <linux/delay.h>
26
27 #include "../common/ngpixis.h"
28 #include "../common/fman.h"
29 #include <fsl_dtsec.h>
30
31 #define EMI_NONE 0xffffffff
32 #define EMI_MASK 0xf0000000
33 #define EMI1_RGMII 0x0
34 #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
35 #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
36 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
37 #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
38 #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
39 #define EMI1_MASK 0xc0000000
40 #define EMI2_MASK 0x30000000
41
42 #define PHY_BASE_ADDR 0x00
43 #define PHY_BASE_ADDR_SLOT5 0x10
44
45 static int mdio_mux[NUM_FM_PORTS];
46
47 static char *mdio_names[16] = {
48 "P4080DS_MDIO0",
49 "P4080DS_MDIO1",
50 NULL,
51 "P4080DS_MDIO3",
52 "P4080DS_MDIO4",
53 NULL, NULL, NULL,
54 "P4080DS_MDIO8",
55 NULL, NULL, NULL,
56 "P4080DS_MDIO12",
57 NULL, NULL, NULL,
58 };
59
60 /*
61 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
62 * that the mapping must be determined dynamically, or that the lane maps to
63 * something other than a board slot.
64 */
65 static u8 lane_to_slot[] = {
66 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
67 };
68
p4080ds_mdio_name_for_muxval(u32 muxval)69 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
70 {
71 return mdio_names[(muxval & EMI_MASK) >> 28];
72 }
73
mii_dev_for_muxval(u32 muxval)74 struct mii_dev *mii_dev_for_muxval(u32 muxval)
75 {
76 struct mii_dev *bus;
77 char *name = p4080ds_mdio_name_for_muxval(muxval);
78
79 if (!name) {
80 printf("No bus for muxval %x\n", muxval);
81 return NULL;
82 }
83
84 bus = miiphy_get_dev_by_name(name);
85
86 if (!bus) {
87 printf("No bus by name %s\n", name);
88 return NULL;
89 }
90
91 return bus;
92 }
93
94 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
board_phy_config(struct phy_device * phydev)95 int board_phy_config(struct phy_device *phydev)
96 {
97 if (phydev->drv->config)
98 phydev->drv->config(phydev);
99 if (phydev->drv->uid == PHY_UID_TN2020) {
100 unsigned long timeout = 1 * 1000; /* 1 seconds */
101 enum srds_prtcl device;
102
103 /*
104 * Wait for the XAUI to come out of reset. This is when it
105 * starts transmitting alignment signals.
106 */
107 while (--timeout) {
108 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
109 if (reg < 0) {
110 printf("TN2020: Error reading from PHY at "
111 "address %u\n", phydev->addr);
112 break;
113 }
114 /*
115 * Note that we've never actually seen
116 * MDIO_CTRL1_RESET set to 1.
117 */
118 if ((reg & MDIO_CTRL1_RESET) == 0)
119 break;
120 udelay(1000);
121 }
122
123 if (!timeout) {
124 printf("TN2020: Timeout waiting for PHY at address %u "
125 " to reset.\n", phydev->addr);
126 }
127
128 switch (phydev->addr) {
129 case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
130 device = XAUI_FM1;
131 break;
132 case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
133 device = XAUI_FM2;
134 break;
135 default:
136 device = NONE;
137 }
138
139 serdes_reset_rx(device);
140 }
141
142 return 0;
143 }
144 #endif
145
146 struct p4080ds_mdio {
147 u32 muxval;
148 struct mii_dev *realbus;
149 };
150
p4080ds_mux_mdio(u32 muxval)151 static void p4080ds_mux_mdio(u32 muxval)
152 {
153 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
154 uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
155 gpioval |= muxval;
156
157 out_be32(&pgpio->gpdat, gpioval);
158 }
159
p4080ds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)160 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
161 int regnum)
162 {
163 struct p4080ds_mdio *priv = bus->priv;
164
165 p4080ds_mux_mdio(priv->muxval);
166
167 return priv->realbus->read(priv->realbus, addr, devad, regnum);
168 }
169
p4080ds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)170 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
171 int regnum, u16 value)
172 {
173 struct p4080ds_mdio *priv = bus->priv;
174
175 p4080ds_mux_mdio(priv->muxval);
176
177 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
178 }
179
p4080ds_mdio_reset(struct mii_dev * bus)180 static int p4080ds_mdio_reset(struct mii_dev *bus)
181 {
182 struct p4080ds_mdio *priv = bus->priv;
183
184 return priv->realbus->reset(priv->realbus);
185 }
186
p4080ds_mdio_init(char * realbusname,u32 muxval)187 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
188 {
189 struct p4080ds_mdio *pmdio;
190 struct mii_dev *bus = mdio_alloc();
191
192 if (!bus) {
193 printf("Failed to allocate P4080DS MDIO bus\n");
194 return -1;
195 }
196
197 pmdio = malloc(sizeof(*pmdio));
198 if (!pmdio) {
199 printf("Failed to allocate P4080DS private data\n");
200 free(bus);
201 return -1;
202 }
203
204 bus->read = p4080ds_mdio_read;
205 bus->write = p4080ds_mdio_write;
206 bus->reset = p4080ds_mdio_reset;
207 sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
208
209 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
210
211 if (!pmdio->realbus) {
212 printf("No bus with name %s\n", realbusname);
213 free(bus);
214 free(pmdio);
215 return -1;
216 }
217
218 pmdio->muxval = muxval;
219 bus->priv = pmdio;
220
221 return mdio_register(bus);
222 }
223
board_ft_fman_fixup_port(void * blob,char * prop,phys_addr_t pa,enum fm_port port,int offset)224 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
225 enum fm_port port, int offset)
226 {
227 if (mdio_mux[port] == EMI1_RGMII)
228 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
229
230 if (mdio_mux[port] == EMI1_SLOT3) {
231 int idx = port - FM2_DTSEC1 + 5;
232 char phy[16];
233
234 sprintf(phy, "phy%d_slot3", idx);
235
236 fdt_set_phy_handle(blob, prop, pa, phy);
237 }
238 }
239
fdt_fixup_board_enet(void * fdt)240 void fdt_fixup_board_enet(void *fdt)
241 {
242 int i;
243
244 /*
245 * P4080DS can be configured in many different ways, supporting a number
246 * of combinations of ethernet devices and phy types. In order to
247 * have just one device tree for all of those configurations, we fix up
248 * the tree here. By default, the device tree configures FM1 and FM2
249 * for SGMII, and configures XAUI on both 10G interfaces. So we have
250 * a number of different variables to track:
251 *
252 * 1) Whether the device is configured at all. Whichever devices are
253 * not enabled should be disabled by setting the "status" property
254 * to "disabled".
255 * 2) What the PHY interface is. If this is an RGMII connection,
256 * we should change the "phy-connection-type" property to
257 * "rgmii"
258 * 3) Which PHY is being used. Because the MDIO buses are muxed,
259 * we need to redirect the "phy-handle" property to point at the
260 * PHY on the right slot/bus.
261 */
262
263 /* We've got six MDIO nodes that may or may not need to exist */
264 fdt_status_disabled_by_alias(fdt, "emi1_slot3");
265 fdt_status_disabled_by_alias(fdt, "emi1_slot4");
266 fdt_status_disabled_by_alias(fdt, "emi1_slot5");
267 fdt_status_disabled_by_alias(fdt, "emi2_slot4");
268 fdt_status_disabled_by_alias(fdt, "emi2_slot5");
269
270 for (i = 0; i < NUM_FM_PORTS; i++) {
271 switch (mdio_mux[i]) {
272 case EMI1_SLOT3:
273 fdt_status_okay_by_alias(fdt, "emi1_slot3");
274 break;
275 case EMI1_SLOT4:
276 fdt_status_okay_by_alias(fdt, "emi1_slot4");
277 break;
278 case EMI1_SLOT5:
279 fdt_status_okay_by_alias(fdt, "emi1_slot5");
280 break;
281 case EMI2_SLOT4:
282 fdt_status_okay_by_alias(fdt, "emi2_slot4");
283 break;
284 case EMI2_SLOT5:
285 fdt_status_okay_by_alias(fdt, "emi2_slot5");
286 break;
287 }
288 }
289 }
290
board_eth_init(struct bd_info * bis)291 int board_eth_init(struct bd_info *bis)
292 {
293 #ifdef CONFIG_FMAN_ENET
294 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
295 int i;
296 struct fsl_pq_mdio_info dtsec_mdio_info;
297 struct tgec_mdio_info tgec_mdio_info;
298 struct mii_dev *bus;
299
300 /* Initialize the mdio_mux array so we can recognize empty elements */
301 for (i = 0; i < NUM_FM_PORTS; i++)
302 mdio_mux[i] = EMI_NONE;
303
304 /* The first 4 GPIOs are outputs to control MDIO bus muxing */
305 out_be32(&pgpio->gpdir, EMI_MASK);
306
307 dtsec_mdio_info.regs =
308 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
309 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
310
311 /* Register the 1G MDIO bus */
312 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
313
314 tgec_mdio_info.regs =
315 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
316 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
317
318 /* Register the 10G MDIO bus */
319 fm_tgec_mdio_init(bis, &tgec_mdio_info);
320
321 /* Register the 6 muxing front-ends to the MDIO buses */
322 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
323 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
324 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
325 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
326 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
327 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
328
329 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
330 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
331 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
332 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
333 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
334
335 #if (CONFIG_SYS_NUM_FMAN == 2)
336 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
337 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
338 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
339 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
340 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
341 #endif
342
343 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
344 int idx = i - FM1_DTSEC1, lane, slot;
345 switch (fm_info_get_enet_if(i)) {
346 case PHY_INTERFACE_MODE_SGMII:
347 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
348 if (lane < 0)
349 break;
350 slot = lane_to_slot[lane];
351 switch (slot) {
352 case 3:
353 mdio_mux[i] = EMI1_SLOT3;
354 fm_info_set_mdio(i,
355 mii_dev_for_muxval(mdio_mux[i]));
356 break;
357 case 4:
358 mdio_mux[i] = EMI1_SLOT4;
359 fm_info_set_mdio(i,
360 mii_dev_for_muxval(mdio_mux[i]));
361 break;
362 case 5:
363 mdio_mux[i] = EMI1_SLOT5;
364 fm_info_set_mdio(i,
365 mii_dev_for_muxval(mdio_mux[i]));
366 break;
367 };
368 break;
369 case PHY_INTERFACE_MODE_RGMII:
370 case PHY_INTERFACE_MODE_RGMII_TXID:
371 case PHY_INTERFACE_MODE_RGMII_RXID:
372 case PHY_INTERFACE_MODE_RGMII_ID:
373 fm_info_set_phy_address(i, 0);
374 mdio_mux[i] = EMI1_RGMII;
375 fm_info_set_mdio(i,
376 mii_dev_for_muxval(mdio_mux[i]));
377 break;
378 default:
379 break;
380 }
381 }
382 bus = mii_dev_for_muxval(EMI1_SLOT5);
383 set_sgmii_phy(bus, FM1_DTSEC1,
384 CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
385
386 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
387 int idx = i - FM1_10GEC1, lane, slot;
388 switch (fm_info_get_enet_if(i)) {
389 case PHY_INTERFACE_MODE_XGMII:
390 lane = serdes_get_first_lane(XAUI_FM1 + idx);
391 if (lane < 0)
392 break;
393 slot = lane_to_slot[lane];
394 switch (slot) {
395 case 4:
396 mdio_mux[i] = EMI2_SLOT4;
397 fm_info_set_mdio(i,
398 mii_dev_for_muxval(mdio_mux[i]));
399 break;
400 case 5:
401 mdio_mux[i] = EMI2_SLOT5;
402 fm_info_set_mdio(i,
403 mii_dev_for_muxval(mdio_mux[i]));
404 break;
405 };
406 break;
407 default:
408 break;
409 }
410 }
411
412 #if (CONFIG_SYS_NUM_FMAN == 2)
413 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
414 int idx = i - FM2_DTSEC1, lane, slot;
415 switch (fm_info_get_enet_if(i)) {
416 case PHY_INTERFACE_MODE_SGMII:
417 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
418 if (lane < 0)
419 break;
420 slot = lane_to_slot[lane];
421 switch (slot) {
422 case 3:
423 mdio_mux[i] = EMI1_SLOT3;
424 fm_info_set_mdio(i,
425 mii_dev_for_muxval(mdio_mux[i]));
426 break;
427 case 4:
428 mdio_mux[i] = EMI1_SLOT4;
429 fm_info_set_mdio(i,
430 mii_dev_for_muxval(mdio_mux[i]));
431 break;
432 case 5:
433 mdio_mux[i] = EMI1_SLOT5;
434 fm_info_set_mdio(i,
435 mii_dev_for_muxval(mdio_mux[i]));
436 break;
437 };
438 break;
439 case PHY_INTERFACE_MODE_RGMII:
440 case PHY_INTERFACE_MODE_RGMII_TXID:
441 case PHY_INTERFACE_MODE_RGMII_RXID:
442 case PHY_INTERFACE_MODE_RGMII_ID:
443 fm_info_set_phy_address(i, 0);
444 mdio_mux[i] = EMI1_RGMII;
445 fm_info_set_mdio(i,
446 mii_dev_for_muxval(mdio_mux[i]));
447 break;
448 default:
449 break;
450 }
451 }
452
453 bus = mii_dev_for_muxval(EMI1_SLOT3);
454 set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
455 bus = mii_dev_for_muxval(EMI1_SLOT4);
456 set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
457
458 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
459 int idx = i - FM2_10GEC1, lane, slot;
460 switch (fm_info_get_enet_if(i)) {
461 case PHY_INTERFACE_MODE_XGMII:
462 lane = serdes_get_first_lane(XAUI_FM2 + idx);
463 if (lane < 0)
464 break;
465 slot = lane_to_slot[lane];
466 switch (slot) {
467 case 4:
468 mdio_mux[i] = EMI2_SLOT4;
469 fm_info_set_mdio(i,
470 mii_dev_for_muxval(mdio_mux[i]));
471 break;
472 case 5:
473 mdio_mux[i] = EMI2_SLOT5;
474 fm_info_set_mdio(i,
475 mii_dev_for_muxval(mdio_mux[i]));
476 break;
477 };
478 break;
479 default:
480 break;
481 }
482 }
483 #endif
484
485 cpu_eth_init(bis);
486 #endif /* CONFIG_FMAN_ENET */
487
488 return pci_eth_init(bis);
489 }
490