1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <cpu_func.h>
9 #include <hang.h>
10 #include <image.h>
11 #include <init.h>
12 #include <log.h>
13 #include <spl.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx8mm_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/arch/ddr.h>
22
23 #include <dm/uclass.h>
24 #include <dm/device.h>
25 #include <dm/uclass-internal.h>
26 #include <dm/device-internal.h>
27
28 #include <power/pmic.h>
29 #include <power/bd71837.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
spl_board_boot_device(enum boot_device boot_dev_spl)33 int spl_board_boot_device(enum boot_device boot_dev_spl)
34 {
35 switch (boot_dev_spl) {
36 case SD2_BOOT:
37 case MMC2_BOOT:
38 return BOOT_DEVICE_MMC1;
39 case SD3_BOOT:
40 case MMC3_BOOT:
41 return BOOT_DEVICE_MMC2;
42 default:
43 return BOOT_DEVICE_NONE;
44 }
45 }
46
spl_dram_init(void)47 static void spl_dram_init(void)
48 {
49 ddr_init(&dram_timing);
50 }
51
spl_board_init(void)52 void spl_board_init(void)
53 {
54 puts("Normal Boot\n");
55 }
56
57 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)58 int board_fit_config_name_match(const char *name)
59 {
60 /* Just empty function now - can't decide what to choose */
61 debug("%s: %s\n", __func__, name);
62
63 return 0;
64 }
65 #endif
66
67 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
68 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
69
70 static iomux_v3_cfg_t const uart_pads[] = {
71 IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
72 IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
73 };
74
75 static iomux_v3_cfg_t const wdog_pads[] = {
76 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
77 };
78
board_early_init_f(void)79 int board_early_init_f(void)
80 {
81 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
82
83 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
84
85 set_wdog_reset(wdog);
86
87 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
88
89 return 0;
90 }
91
power_init_board(void)92 static int power_init_board(void)
93 {
94 struct udevice *dev;
95 int ret;
96
97 ret = pmic_get("pmic@4b", &dev);
98 if (ret == -ENODEV) {
99 puts("No pmic\n");
100 return 0;
101 }
102 if (ret != 0)
103 return ret;
104
105 /* decrease RESET key long push time from the default 10s to 10ms */
106 pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
107
108 /* unlock the PMIC regs */
109 pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
110
111 /* increase VDD_SOC to typical value 0.85v before first DRAM access */
112 pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
113
114 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
115 pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
116
117 #ifndef CONFIG_IMX8M_LPDDR4
118 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
119 pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
120 #endif
121
122 /* lock the PMIC regs */
123 pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
124
125 return 0;
126 }
127
board_init_f(ulong dummy)128 void board_init_f(ulong dummy)
129 {
130 struct udevice *dev;
131 int ret;
132
133 arch_cpu_init();
134
135 init_uart_clk(1);
136
137 board_early_init_f();
138
139 timer_init();
140
141 preloader_console_init();
142
143 /* Clear the BSS. */
144 memset(__bss_start, 0, __bss_end - __bss_start);
145
146 ret = spl_early_init();
147 if (ret) {
148 debug("spl_early_init() failed: %d\n", ret);
149 hang();
150 }
151
152 ret = uclass_get_device_by_name(UCLASS_CLK,
153 "clock-controller@30380000",
154 &dev);
155 if (ret < 0) {
156 printf("Failed to find clock node. Check device tree\n");
157 hang();
158 }
159
160 enable_tzc380();
161
162 power_init_board();
163
164 /* DDR initialization */
165 spl_dram_init();
166
167 board_init_r(NULL, 0);
168 }
169